Patrick Chase (patrickjchase.delete@this.gmail.com) on July 3, 2013 9:04 pm wrote:
> Symmetry (someone.delete@this.somewhere.com) on July 3, 2013 7:14 am wrote:
> > But even then you have to worry about having a consistant state in
> > the event of an interrupt and that means a storage requirement that really does
> > grow with the width of the vector.
>
> Yep. The fact that general-purpose CPU architectures like x86, ARM, and POWER require
> precise interrupts adds a nontrivial cost penalty if you want to do any sort of
> reordering.
>
> The way Intel dealt with this in Xeon Phi is by redefining the architectural exception
> model - There are no traps for floating point exceptions. If you want to know if
> something bad happened then you have to look at the corresponding flags.

I should probably have been more precise in my wording here: Xeon Phi has both scalar x87 FP (carried over from its P54-derived scalar core) and 512-bit SIMD FP ISA.

The x87 FPU supports full IEEE FP semantics including exception traps. The SIMD units do not generate traps, period.

If you request strict FP exceptions then the compiler will only generate x87 code, at which point you probably would have been better off with a conventional CPU (AVX in SB/IB/Haswell can generate traps on FP exceptions).

Intel does a pretty good job of explaining the microarchitecture and specificallywhy the vector pipes can't raise exceptions towards the bottom of the "Core Pipeline Stages" section here:

http://software.intel.com/en-us/articles/intel-xeon-phi-core-micro-architecture