By: Michael S (already5chosen.delete@this.yahoo.com), July 5, 2013 6:41 am
Room: Moderated Discussions
Etienne (etienne_lorrain.delete@this.yahoo.fr) on July 5, 2013 3:14 am wrote:
> Sorry to switch subject, I have a question I do not know where to ask:
> (please note I am not a hardware specialist)
>
> A processor with two layer cache writes a byte to zero, none of the memory is in cache.
> So the processor system looks for the address in layer 1 cache, do not find it, looks
> in layer 2 cache, do not find it, instruct the layer 2 cache to fetch the memory.
Correct, in specific case of Silvermont, but not in general. For example, it's not true in AMD K7/K8/K10 families, where the line from memory or from L3 cache is loaded directly into L1D cache, bypassing L2.
> When the layer 1 cache line is filled, the instruction to clear the byte executes.
> If at that point
What you mean by "at that point" ? In typical scenario it happens much later.
Except, of course, when your L1D caches is write-through like on Intel Netburst, AMD Bulldozer and majority of IBM zArch cores.
> both layer cache are no more needed and evicted, what size is written
> back to memory: a layer 1 cache line or a layer 2 cache line (which would be a lot bigger).
First, I am not aware of the processors in which L2 line is "a lot bigger". All popular PC processors of today have 64-byte cache lines in both L1D and L2.
In the past there were processors with 128-byte L2 lines, but I wouldn't consider 2x difference as "a lot".
> In other words, is there "dirty bits" for every layer 1 cache line inside the layer 2 cache?
>
Yes, when there still were 128-byte lines in L2 caches they were managed like 2 64-byte segments, with 2 separate dirty bits.
> Thanks. Pointers to documentation welcomed.
Intel optimization reference manuals tend to provide all the information you are asking for. That is, for mainline cores. For Bonnel/Saltwell/Silvermont, not so much :(
> Sorry to switch subject, I have a question I do not know where to ask:
> (please note I am not a hardware specialist)
>
> A processor with two layer cache writes a byte to zero, none of the memory is in cache.
> So the processor system looks for the address in layer 1 cache, do not find it, looks
> in layer 2 cache, do not find it, instruct the layer 2 cache to fetch the memory.
Correct, in specific case of Silvermont, but not in general. For example, it's not true in AMD K7/K8/K10 families, where the line from memory or from L3 cache is loaded directly into L1D cache, bypassing L2.
> When the layer 1 cache line is filled, the instruction to clear the byte executes.
> If at that point
What you mean by "at that point" ? In typical scenario it happens much later.
Except, of course, when your L1D caches is write-through like on Intel Netburst, AMD Bulldozer and majority of IBM zArch cores.
> both layer cache are no more needed and evicted, what size is written
> back to memory: a layer 1 cache line or a layer 2 cache line (which would be a lot bigger).
First, I am not aware of the processors in which L2 line is "a lot bigger". All popular PC processors of today have 64-byte cache lines in both L1D and L2.
In the past there were processors with 128-byte L2 lines, but I wouldn't consider 2x difference as "a lot".
> In other words, is there "dirty bits" for every layer 1 cache line inside the layer 2 cache?
>
Yes, when there still were 128-byte lines in L2 caches they were managed like 2 64-byte segments, with 2 separate dirty bits.
> Thanks. Pointers to documentation welcomed.
Intel optimization reference manuals tend to provide all the information you are asking for. That is, for mainline cores. For Bonnel/Saltwell/Silvermont, not so much :(
