By: Etienne (etienne_lorrain.delete@this.yahoo.fr), July 5, 2013 8:15 am
Room: Moderated Discussions
Michael S (already5chosen.delete@this.yahoo.com) on July 5, 2013 6:41 am wrote:
> Etienne (etienne_lorrain.delete@this.yahoo.fr) on July 5, 2013 3:14 am wrote:
> > Sorry to switch subject, I have a question I do not know where to ask:
> > ...
> > When the layer 1 cache line is filled, the instruction to clear the byte executes.
> > If at that point
>
> What you mean by "at that point" ? In typical scenario it happens much later.
I meant software has decided to do something else and needs another cache line,
that one is reused.
> First, I am not aware of the processors in which L2 line is "a lot bigger".
Thanks for pointing out my error, I was thinking L2 lines were bigger than L1 lines.
> Intel optimization reference manuals tend to provide all the information you are asking
> for. That is, for mainline cores. For Bonnel/Saltwell/Silvermont, not so much :(
lots to read there.
Thanks.
> Etienne (etienne_lorrain.delete@this.yahoo.fr) on July 5, 2013 3:14 am wrote:
> > Sorry to switch subject, I have a question I do not know where to ask:
> > ...
> > When the layer 1 cache line is filled, the instruction to clear the byte executes.
> > If at that point
>
> What you mean by "at that point" ? In typical scenario it happens much later.
I meant software has decided to do something else and needs another cache line,
that one is reused.
> First, I am not aware of the processors in which L2 line is "a lot bigger".
Thanks for pointing out my error, I was thinking L2 lines were bigger than L1 lines.
> Intel optimization reference manuals tend to provide all the information you are asking
> for. That is, for mainline cores. For Bonnel/Saltwell/Silvermont, not so much :(
lots to read there.
Thanks.