By: Patrick Chase (patrickjchase.delete@this.gmail.com), July 8, 2013 10:02 am
Room: Moderated Discussions
Etienne (etienne_lorrain.delete@this.yahoo.fr) on July 8, 2013 3:10 am wrote:
> Patrick Chase (patrickjchase.delete@this.gmail.com) on July 6, 2013 12:08 pm wrote:
> > Cortex A8, along with several older and/or lower-end ARM cores.
>
> Probably my experience of having a DMA moving memory a lot quicker than the CPU (in a
> booting context to test/initialize memory) is due to me using such a Cortex A8 and
> previously some PowerPC embedded processors...
Embedded PPCs like the 440 typically have write-back L1s with configurable allocation policies - They can be either allocate-on-read or allocate-on-read/write depending on page properties and a global control register bit (SWOA in MMUCR). As noted in other posts you would want to use those for workloads that do a lot of one-time (no temporal locality) write-only accesses.
> Patrick Chase (patrickjchase.delete@this.gmail.com) on July 6, 2013 12:08 pm wrote:
> > Cortex A8, along with several older and/or lower-end ARM cores.
>
> Probably my experience of having a DMA moving memory a lot quicker than the CPU (in a
> booting context to test/initialize memory) is due to me using such a Cortex A8 and
> previously some PowerPC embedded processors...
Embedded PPCs like the 440 typically have write-back L1s with configurable allocation policies - They can be either allocate-on-read or allocate-on-read/write depending on page properties and a global control register bit (SWOA in MMUCR). As noted in other posts you would want to use those for workloads that do a lot of one-time (no temporal locality) write-only accesses.
