Paul A. Clayton (paaronclayton.delete@this.gmail.com) on July 30, 2013 11:03 am wrote:
> Sebastian Soeiro (sebastian_2896.delete@this.hotmail.com) on July 30, 2013 9:34 am wrote:
> > Just a quick question; wondering if anyone could help me out.
> >
> > In most architectures, where is the TLB for the RAM held? I used to think it took a small partition
> > of the RAM itself as the TLB, but further reading makese doubt it's exact location.
> >
> > Can anyone tell me where the TLB for the RAM is located?
>
> Page tables are located in main memory. TLBs are caches of these page tables providing low latency
> and high throughput access to translation (and permission) information. In order to provide such performance,
> they are located close to the processor core and use faster memory technology than DRAM.
>
> Because TLBs are caches, requests for translation information can miss, requiring the loading of
> this information from the page table in memory. (This loading can be done automatically by hardware--as
> in x86, ARM, and version 5 of MIPS--by generating an exception which is handled by software--as in
> earlier versions of MIPS--or by a combination of the two mechanisms--as in at least some implementations
> of Itanium which only handle a single step of page table look-up in hardware.)
>
> Complicating this description, there is a concept called a software TLB in which a portion of main
> memory caches part of the page table. Software TLBs allow an architecture to define a specific format
> for an in-memory table from which hardware can load entries into the hardware TLBs without forcing
> operating systems to use this format for the entire page table. To provide faster access, they typically
> provide a look-up mechanism with fewer dependent steps than multi-level page tables or linear page
> tables. (The software TLB technique has also been used for software-loaded [hardware] TLBs.) Software
> TLBs are somewhat out of fashion for a variety of good (and some more incidental) reasons.
>
> Anyway, (non-software) TLBs are associated with the other caches of a processor and are not in main memory.

Thank you very much for your answer,

So page tables are stored in memory and there are TLBs to manage those tables currently being used it seems.

Just to clarify, this explanation is only for the TLB for the main memory, right? The L1DTLB or L3 TLB have no knowledge of whats going on in main memory, correct?

Also, if the TLB is on-die; where is it? Is it integrated into the IMC or another location?

Thank you again for your help!