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Article: Silvermont, Intel's Low Power Architecture
By: Paul A. Clayton (paaronclayton.delete@this.gmail.com), July 31, 2013 3:11 pm
Room: Moderated Discussions
Sebastian Soeiro (sebastian_2896.delete@this.hotmail.com) on July 31, 2013 2:15 pm wrote:
[snip]

> - The TLB lies in the store components of a core. (I know you said one TLB per CPU... but then
> you said that the TLB lies in the store components, so you must've meant core, correct?)

To get an idea of where TLBs are physically located, you can take a look at CPU floorplans (doing a web image search for "CPU core floorplan" should provide some interesting viewing). Hans de Vries has a number of such images (and some articles with analysis). The following is probably a helpful example: http://www.chip-architect.com/news/K8L_floorplan.jpg

> - There is not multiple TLBs (like I thought) unless they are tertiary TLBs
> to the primary TLB, or a microTLB to help sort out the primary TLB.

TLBs are not associated with levels of the (ordinary) cache, but like cache can be divided into multiple levels and be shared or private between instruction and data accesses (and even between different cores).

> - The TLB is just a cache of the last acceses to information; their translations and permissions.

Yep! The "authoritative" source for such information is the page table(s) and TLBs are caches of page table information. (Intel calls the structure which stores internal node entries in its multi-level page table Paging-Structure Caches, so Intel might view a TLB as only holding Page Table Entries and not any Page Directory Entries and other parts of the hierarchical page table. Since Intel has not implemented a structure which caches both types of page table components, it is not obvious what Intel would call such a hardware structure. I seem to recall Robert Wessel [on the comp.arch newsgroup, I think] mentioning some time ago that some implementation of IBM mainframes did have TLBs that cached more than just PTEs--and called them TLBs.)

> - NO caches have a TLB solely for them; though all caches have a page table or multiple in them

The L1 TLBs are somewhat tightly bound to the L1 caches in typical processors (that have TLBs) to allow minimal latency in L1 cache accesses. However, there is typically not a special TLB for the L2 cache nor another for the L3 cache.

Page tables are conceptually stored in main memory, but like other parts of main memory can be found in caches. (Theoretically, pages of a page table can even be paged out to swap like other memory.)

In a typical system, each software process has a separate virtual address space requiring a separate page table. (Threads within a process share address space/page table.) The OS typically takes a portion of each process' total address space as a virtual memory region shared across the system. Mechanisms exist to to avoid duplicating all of the information in this region (e.g., the ARM ISA defines a global address space with a mask determining what accesses are within the per-process address space and which are in the global address space). (Eep! Excess digression!)

> - The TLB uses these page tables to track what is inside a cache/RAM and
> uses the table to translate virtual addresses to physical addresses.

The TLBs are (typically) not concerned with what is present in the caches and only provide information to translate virtual addresses to physical address and some other metadata like permissions, accessed and dirty bits, cache write-through/write-back behavior, etc. Each virtual address page (typically an aligned chunk of memory about 4KiB in size) is associated with a Page Table Entry (typically 64-bits in size for 64-bit address spaces). The page table entries are stored in the page table and the information is cached in the TLBs.

A PTE can have its validity bit cleared to indicate that the page associated with the virtual address is not in memory, but it is the operating system software that handles such. (Some specifics of how the TLB handles invalid PTEs depend on the choices made by the developers of the architecture, but obviously any non-speculative access must generate an exception so that the OS can load the appropriate page and set the valid bit of the PTE.)

> Did I... Get it right? I really hope so, this is going in
> a completely different direction than I thought it would.

It looks like you have got it mostly right.

As with any area of knowledge, the more one learns, the more one discovers how much one does not know (and how interconnected knowledge is).

(In my reading about computer architecture, I have concentrated somewhat on caches and TLBs because these areas seem to be somewhat more accessible--lack of circuit design or programming knowledge is not a major issue for reading most of the academic papers--, the way they impact performance is relatively straightforward, and they have a significant impact on performance and power efficiency.)
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              How Does Silvermont Compare To A15?Ashraf Eassa2013/05/15 10:59 AM
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                                                  Silvermont architecture in-depth articleDavid Kanter2013/06/02 10:10 PM
                                                    Silvermont architecture in-depth articleSebastian Soeiro2013/06/03 07:25 AM
                                              Silvermont architecture in-depth articlerwessel2013/06/02 11:09 PM
                                                Silvermont architecture in-depth articleSebastian Soeiro2013/06/03 08:59 AM
                                                  Silvermont architecture in-depth articlerwessel2013/06/03 09:51 AM
                                                    Silvermont architecture in-depth articleSebastian Soeiro2013/06/04 05:31 PM
                                      Silvermont architecture in-depth articlerwessel2013/05/31 02:20 PM
                                        Silvermont architecture in-depth articleSebastian Soeiro2013/05/31 05:59 PM
                                          Silvermont architecture in-depth articlerwessel2013/05/31 08:02 PM
                                            Silvermont architecture in-depth articleSebastian Soeiro2013/05/31 08:13 PM
                                            Quibbling on multithreadingPaul A. Clayton2013/06/01 09:11 AM
                                              Quibbling on multithreadingrwessel2013/06/02 10:54 PM
                                                Exploiting for SMT was my "contribution"Paul A. Clayton2013/06/03 03:53 AM
                                            Silvermont architecture in-depth articleMichael S2013/06/01 09:49 AM
                        Silvermont architecture in-depth articleRicardo B2013/05/30 03:41 PM
                          Didn't notice how this was to be organized...Sebastian Soeiro2013/05/30 06:55 PM
          Silvermont, not Saltwell? (NT)papapapa2013/05/28 03:33 PM
            Of course. Not enough sleep. (NT)Ricardo B2013/05/29 01:27 PM
  No out-of-order in FP cluster of silvermont?anon2013/06/28 02:27 AM
    No out-of-order in FP cluster of silvermont?Michael S2013/06/28 03:52 AM
      No out-of-order in FP cluster of silvermont?Exophase2013/06/28 12:54 PM
        No out-of-order in FP cluster of silvermont?Michael S2013/06/29 10:21 AM
          No out-of-order in FP cluster of silvermont?Exophase2013/06/29 08:07 PM
      No out-of-order in FP cluster of silvermont?Linus Torvalds2013/06/29 11:22 AM
        No out-of-order in FP cluster of silvermont?anon2013/06/29 04:26 PM
          No out-of-order in FP cluster of silvermont?EduardoS2013/06/29 05:50 PM
            No out-of-order in FP cluster of silvermont?anon2013/06/29 08:15 PM
              No out-of-order in FP cluster of silvermont?EduardoS2013/06/29 08:31 PM
                No out-of-order in FP cluster of silvermont?anon2013/06/30 01:53 AM
                  No out-of-order in FP cluster of silvermont?EduardoS2013/06/30 04:24 AM
                    No out-of-order in FP cluster of silvermont?anon2013/06/30 09:41 AM
                      No out-of-order in FP cluster of silvermont?EduardoS2013/06/30 12:26 PM
                        No out-of-order in FP cluster of silvermont?anon2013/06/30 11:32 PM
                          No out-of-order in FP cluster of silvermont?EduardoS2013/07/01 04:40 PM
                            No out-of-order in FP cluster of silvermont?anon2013/07/01 05:44 PM
                            No out-of-order in FP cluster of silvermont?Michael S2013/07/02 04:40 AM
                              No out-of-order in FP cluster of silvermont?Exophase2013/07/02 08:03 AM
                              No out-of-order in FP cluster of silvermont?EduardoS2013/07/02 04:20 PM
                          No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 08:25 AM
                      No out-of-order in FP cluster of silvermont?Etienne2013/07/02 03:36 AM
                        No out-of-order in FP cluster of silvermont?anon2013/07/02 06:13 AM
                          No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 09:03 AM
                            No out-of-order in FP cluster of silvermont?anon2013/07/02 03:12 PM
                              No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 03:43 PM
                                No out-of-order in FP cluster of silvermont?anon2013/07/02 04:47 PM
                                  No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 06:36 PM
                                    No out-of-order in FP cluster of silvermont?anon2013/07/02 08:03 PM
                                      No out-of-order in FP cluster of silvermont?Symmetry2013/07/03 06:14 AM
                                        No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/03 08:04 PM
                                          No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/04 02:23 AM
                        No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 09:01 AM
                          No out-of-order in FP cluster of silvermont?Etienne2013/07/03 02:26 AM
                            layer 2 cache behaviourEtienne2013/07/05 02:14 AM
                              layer 2 cache behaviourMichael S2013/07/05 05:41 AM
                                layer 2 cache behaviourEtienne2013/07/05 08:15 AM
                              layer 2 cache behaviourPatrick Chase2013/07/05 10:37 AM
                                layer 2 cache behaviourMichael S2013/07/06 09:57 AM
                                  layer 2 cache behaviourPatrick Chase2013/07/06 11:08 AM
                                    layer 2 cache behaviourPatrick Chase2013/07/06 11:19 AM
                                    layer 2 cache behaviourEtienne2013/07/08 02:10 AM
                                      layer 2 cache behaviourPatrick Chase2013/07/08 09:02 AM
                                  layer 2 cache behaviourPatrick Chase2013/07/06 01:15 PM
                                  layer 2 cache behaviourUngo2013/07/09 02:24 PM
                      No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 07:43 AM
                  No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 07:34 AM
                    No out-of-order in FP cluster of silvermont?anon2013/07/02 03:15 PM
            No out-of-order in FP cluster of silvermont?none2013/06/30 04:03 AM
              No out-of-order in FP cluster of silvermont?EduardoS2013/06/30 04:45 AM
                No out-of-order in FP cluster of silvermont?none2013/06/30 05:28 AM
                  No out-of-order in FP cluster of silvermont?EduardoS2013/06/30 12:27 PM
        No out-of-order in FP cluster of silvermont?x2013/06/30 02:54 AM
          No out-of-order in FP cluster of silvermont?Foo_2013/06/30 05:15 AM
        No out-of-order in FP cluster of silvermont?rwessel2013/06/30 09:11 PM
          No out-of-order in FP cluster of silvermont?Linus Torvalds2013/07/01 12:40 PM
            No out-of-order in FP cluster of silvermont?Patrick Chase2013/07/02 09:35 AM
              No out-of-order in FP cluster of silvermont?Linus Torvalds2013/07/02 10:18 AM
            FPU in integer codes2013/07/02 10:38 AM
              FPU in integer codesPatrick Chase2013/07/02 10:56 AM
              FPU in integer codesLinus Torvalds2013/07/02 11:12 AM
                FPU in integer codesPatrick Chase2013/07/02 11:34 AM
                  FPU in integer codesLinus Torvalds2013/07/02 12:55 PM
        No out-of-order in FP cluster of silvermont?2013/06/30 10:42 PM
          No out-of-order in FP cluster of silvermont?bakaneko2013/07/03 02:54 AM
        What about integer SIMD?Exophase2013/06/30 11:44 PM
          What about integer SIMD?anon2013/07/01 12:45 AM
            What about integer SIMD?Michael S2013/07/01 07:57 AM
              What about integer SIMD?rwessel2013/07/01 02:39 PM
                What about integer SIMD?Michael S2013/07/01 03:11 PM
                  What about integer SIMD?EduardoS2013/07/01 05:04 PM
                    What about integer SIMD?Michael S2013/07/01 11:32 PM
          What about integer SIMD?hi2013/07/01 07:15 AM
            What about integer SIMD?Exophase2013/07/01 09:50 AM
            What about integer SIMD?David Kanter2013/07/02 12:20 PM
              What about integer SIMD?hi2013/07/02 02:48 PM
                What about integer SIMD?David Kanter2013/07/04 02:19 PM
  Silvermont architecture in-depth articleSebastian Soeiro2013/07/30 08:34 AM
    TLBs are caches of page tablesPaul A. Clayton2013/07/30 10:03 AM
      TLBs are caches of page tablesSebastian Soeiro2013/07/30 12:18 PM
        TLBs are caches of page tablesPaul A. Clayton2013/07/30 02:59 PM
          TLBs are caches of page tablesSebastian Soeiro2013/07/30 04:27 PM
            TLBs are caches of page tablesrwessel2013/07/30 06:01 PM
              TLBs are caches of page tablesSebastian Soeiro2013/07/31 01:15 PM
                Floorplan images show physical locationsPaul A. Clayton2013/07/31 03:11 PM
                  Floorplan images show physical locationsSebastian Soeiro2013/07/31 08:12 PM
                    Floorplan images show physical locationsrwessel2013/07/31 11:21 PM
                      Floorplan images show physical locationsSebastian Soeiro2013/08/02 11:58 AM
                        Floorplan images show physical locationsAntti-Ville Tuunainen2013/08/02 01:09 PM
                        Floorplan images show physical locationsStubabe2013/08/02 06:49 PM
                          Floorplan images show physical locationsSebastian Soeiro2013/08/03 07:23 AM
                            Floorplan images show physical locationsrwessel2013/08/03 10:16 PM
                            Floorplan images show physical locationsMelody Speer2013/08/04 03:11 AM
                              Floorplan images show physical locationsSebastian Soeiro2013/08/04 04:42 PM
                                Floorplan images show physical locationsrwessel2013/08/04 09:58 PM
                                  Floorplan images show physical locationsSebastian Soeiro2013/08/07 02:33 PM
                                    Floorplan images show physical locationsrwessel2013/08/08 12:03 PM
                                      Floorplan images show physical locationsSebastian Soeiro2013/08/11 08:20 AM
                                        Page tables are set up by the OSPaul A. Clayton2013/08/11 12:25 PM
                                          Page tables are set up by the OSSebastian Soeiro2013/08/16 07:43 PM
                                            Multilevel page table formatPaul A. Clayton2013/08/17 10:18 AM
                                              Multilevel page table formatSebastian Soeiro2013/08/19 02:28 PM
                                                Multilevel page table formatrwessel2013/08/19 11:08 PM
                                                  Multilevel page table formatSebastian Soeiro2013/08/22 03:52 PM
                                                    Multilevel page table formatTREZA2013/08/22 04:30 PM
                                                    Multilevel page table formatrwessel2013/08/23 09:58 PM
                                                      Multilevel page table formatSebastian Soeiro2013/08/25 07:20 AM
                TLBs are caches of page tablesrwessel2013/07/31 11:41 PM
                  TLBs are caches of page tablesSebastian Soeiro2013/08/02 11:51 AM
                    TLBs are caches of page tablesrwessel2013/08/02 05:55 PM
  Silvermont instruction schedulingHugo Décharnes2013/10/02 02:25 AM
    Silvermont instruction schedulingMichael S2013/10/02 03:29 AM
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