By: Michael S (already5chosen.delete@this.yahoo.com), October 2, 2013 4:29 am
Room: Moderated Discussions
First Name Last Name (hdecharn.delete@this.hotmail.fr) on October 2, 2013 3:25 am wrote:
> Hi,
> I can see that allocate-rename and shedule stages take three cycles. Is it
> possible to use the result of an execution unit on the next clock cycle? (Id
> est: is there any forwarding logic or does it require a one cycle stall?)
>
Instruction latencies as seen by software provided in section 15.5 of Intel Optimization reference manual.
http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf
Majority of integer register-to-register instructions has latency=1, i.e. no stall.
Pay attention, the "other" link appearing on many Intel web pages points to outdated manual that does not contain Silvermont data:
http://www.intel.com/content/dam/doc/manual/64-ia-32-architectures-optimization-manual.pdf
> Hi,
> I can see that allocate-rename and shedule stages take three cycles. Is it
> possible to use the result of an execution unit on the next clock cycle? (Id
> est: is there any forwarding logic or does it require a one cycle stall?)
>
Instruction latencies as seen by software provided in section 15.5 of Intel Optimization reference manual.
http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf
Majority of integer register-to-register instructions has latency=1, i.e. no stall.
Pay attention, the "other" link appearing on many Intel web pages points to outdated manual that does not contain Silvermont data:
http://www.intel.com/content/dam/doc/manual/64-ia-32-architectures-optimization-manual.pdf