By: Patrick Chase (patrickjchase.delete@this.gmail.com), August 15, 2013 9:01 pm
Room: Moderated Discussions
Time to nit-pick myself...
Patrick Chase (patrickjchase.delete@this.gmail.com) on August 15, 2013 8:04 pm wrote:
> For example, they could stop renaming the condition register in some future OoO uarch
> and thereby force all predicated 32-bit code to execute in-order through the backend.
Not renaming the condition register would serialize write-after-write (WAW) and write-after-read (WAR) dependencies. If you look at how predication is typically used in ARM code, the lifetime of a given condition value is quite short and WAW/WAR dependencies on the condition register are common. Not renaming the conditions would therefore force common usage idioms to execute in-order through the backend. It would (obviously) not force *all* predicated code to do so.
Patrick Chase (patrickjchase.delete@this.gmail.com) on August 15, 2013 8:04 pm wrote:
> For example, they could stop renaming the condition register in some future OoO uarch
> and thereby force all predicated 32-bit code to execute in-order through the backend.
Not renaming the condition register would serialize write-after-write (WAW) and write-after-read (WAR) dependencies. If you look at how predication is typically used in ARM code, the lifetime of a given condition value is quite short and WAW/WAR dependencies on the condition register are common. Not renaming the conditions would therefore force common usage idioms to execute in-order through the backend. It would (obviously) not force *all* predicated code to do so.