By: Patrick Chase (patrickjchase.delete@this.gmail.com), August 18, 2013 4:55 am
Room: Moderated Discussions
Michael S (already5chosen.delete@this.yahoo.com) on August 17, 2013 2:55 pm wrote:
> > Why do you think that ARM decided that their 64-bit version will have 32
> > general purpose registers (well, 31 plus a dedicated '0' register)?
>
> The only reason I can think about - ARM thinks about possibility of wide (4-ways
> or more) in-order implementation in the future.
ARM's wide implmentations are all OoO with renaming, so those don't/won't benefit very much from more architectural registers. The only way "wider implementation" explains more GPRs is if they're planning to do something like AXP-21164.
> For both AArch64 uArchs disclosed
> so far the benefit of 32 GPRs would be very close to zero.
> 32 SIMD/FP registers is another story. Those are going to help immediately.
People run imaging/audio loads on ARM cores all the time, and those will benefit from the increase in GPRs. As you point out, they'll benefit even more from the extra Neon regs, but not all such workloads are regular for SIMD...
> > Why do you think that ARM decided that their 64-bit version will have 32
> > general purpose registers (well, 31 plus a dedicated '0' register)?
>
> The only reason I can think about - ARM thinks about possibility of wide (4-ways
> or more) in-order implementation in the future.
ARM's wide implmentations are all OoO with renaming, so those don't/won't benefit very much from more architectural registers. The only way "wider implementation" explains more GPRs is if they're planning to do something like AXP-21164.
> For both AArch64 uArchs disclosed
> so far the benefit of 32 GPRs would be very close to zero.
> 32 SIMD/FP registers is another story. Those are going to help immediately.
People run imaging/audio loads on ARM cores all the time, and those will benefit from the increase in GPRs. As you point out, they'll benefit even more from the extra Neon regs, but not all such workloads are regular for SIMD...
