By: Patrick Chase (patrickjchase.delete@this.gmail.com), August 21, 2013 8:37 am
Room: Moderated Discussions
Doug S (foo.delete@this.bar.bar) on August 20, 2013 10:47 pm wrote:
> mas (a.delete@this.b.com) on August 20, 2013 5:53 pm wrote:
> > MIPS brought out 64-bit cores 22 years ago and in the final SGI RS models their ipc
> > in SpecCPU was second only to Itanium 2 so their 'heavy duty 64-bit server heritage'
> > is not as bad as you
>
> Oh boy, not the IPC argument. The favorite defense of those defending an indefensible > position on RWT. The Itanium's "superior" IPC was talked about by a certain someone
> for years, fat lot of good that did it as it is now what it was originally designed
> as by HP two decades ago - PA-RISC 3.0.
I think there's also an element of "engineering snobbery" at play here on RWT. I recall in particular a recent post where wilco criticized the new 2.3 GHz Krait as "not as interesting" as A15 because it's simpler/narrower and a speed demon. For some reason a lot of people just don't appreciate a simple[r] microarchitecture that gets the key things (L0/L1 D$ load->use latency, cough).
> mas (a.delete@this.b.com) on August 20, 2013 5:53 pm wrote:
> > MIPS brought out 64-bit cores 22 years ago and in the final SGI RS models their ipc
> > in SpecCPU was second only to Itanium 2 so their 'heavy duty 64-bit server heritage'
> > is not as bad as you
>
> Oh boy, not the IPC argument. The favorite defense of those defending an indefensible > position on RWT. The Itanium's "superior" IPC was talked about by a certain someone
> for years, fat lot of good that did it as it is now what it was originally designed
> as by HP two decades ago - PA-RISC 3.0.
I think there's also an element of "engineering snobbery" at play here on RWT. I recall in particular a recent post where wilco criticized the new 2.3 GHz Krait as "not as interesting" as A15 because it's simpler/narrower and a speed demon. For some reason a lot of people just don't appreciate a simple[r] microarchitecture that gets the key things (L0/L1 D$ load->use latency, cough).