David Kanter (dkanter.delete@this.realworldtech.com) on August 21, 2013 1:27 pm wrote:
> Second, I'm very curious about your statement regarding address space limitations.
>
> My understanding is that generally things get uncomfortable when your physical
> memory is close to half the virtual address space. You're claiming that it is
> problematic when physical memory 0.1*VAS.
>
> Could you explain that a bit more thoroughly, I'd particularly appreciate
> concrete examples and/or more info about the workloads.

I have no idea where the previous poster was coming from, but I know of embedded systems that get into trouble when physical memory is larger than ~1/8 of the virtual address space.

Where this typically arises is in systems that do not provide cache coherency for I/O devices. In that case it's convenient (but not necessary) for the OS to have multiple "views" of physical memory with different cachability attributes. If you have a system with 4 such views, and if you need 1/2 of the virtual address space for application memory, then that leaves you with (1/2)*(1/4)=1/8 of the virtual address space per view.

Such a partitioning is actual baked into the MIPS32 memory map (the kseg[012] views, which range from 512-1024 MB in size). When this is done with other architectures it's typically implemented either in the bus fabric, or via MPU/MMU configuration.

-- Patrick