mas (mas769.delete@this.hotmail.com) on August 22, 2013 3:34 am wrote:
> none (none.delete@this.none.com) on August 22, 2013 2:30 am wrote:
> > mas (mas769.delete@this.hotmail.com) on August 22, 2013 2:11 am wrote:
> > [...]
> > > e.g. proAptiv is quad-issue and multi-threaded and half the die size of A15
> > > and performs slightly better in single-thread. It is waiting in the wings.
> >
> > Better on what benchmark? Measured on what silicon?
> >
> > MIPS claims 4.4 CoreMark/MHz on preliminary RTL. Too bad A15 production
> > silicon already exceeds that with 9.36 CoreMark/MHz for 2 threads.
> >
> > I hope for their own good they won't wait too long in the wings :-)
> >
> > Refs:
> > - http://www.imgtec.com/mips/mips-proaptiv.asp
> > - entry 1480 of http://www.eembc.org/coremark/index.php
>
> see entry 1495 and proAptiv gets 5.1 CoreMark/MHz for a single thread. Like I said, slightly better.

I had missed that entry, thanks! I'm disappointed that 6 months after announcing FPGA, they are still using FPGA to provide results. I wonder why they didn't make an eASIC or a real testchip. Anyway it looks like they either improved their micro arch or the compiler (the latter being more likely).

Note that I don't think CoreMark score would be distorted too much by the typically unbalanced memory system of FPGA (in that particular case they used DDR2 running at half the frequency of the FPGA, which is unrealistic if the chip is indeed supposed to run at more than 1.5 GHz) given that the whole dataset fits in 32 KB Dcache.

Can't wait to see larger benchmarks :)