Paul A. Clayton (paaronclayton.delete@this.gmail.com) on August 21, 2013 3:59 pm wrote:
> Patrick Chase (patrickjchase.delete@this.gmail.com) on August 21, 2013 12:47 pm wrote:
> [snip]
> > A15 L1 is also 32KB, but 4-way. Set size is therefore 8KB, which is larger than the minimum page size. The
> > cache must therefore behave as though physically indexed
> > to comply with ARMv7. As I noted in my previous post,
> > this can be implemented either by doing TLB lookup before cache lookup, or by doing color prediction.
>
> One can do what AMD did with Athlon of using the virtual address to provide a "color
> prediction" and probing alternate way groups/colors on a miss (and moving any cache
> line that hits in an alternate way group to the currently used way group).
>
> (I am hesitant to call such prediction. Technically, it is prediction, but it is an
> extremely simple form of prediction, very much like pseudo-associativity is
> technically a form of way prediction.)

Or like the backward-taken, forward-not-taken heuristic is technically a form of branch prediction.

IMO anything that involves speculation and requires detection/recovery from mispredicts constitutes prediction, no matter how lame the prediction algorithm may be. By that argument Athlon's scheme is prediction.