By: Brett (ggtgp.delete@this.yahoo.com), September 8, 2013 7:48 pm
Room: Moderated Discussions
David Kanter (dkanter.delete@this.realworldtech.com) on September 8, 2013 5:06 pm wrote:
> > As the Renesas RX family expands up the performance ramp I fully expect Renesas to drop in
> > a x86 decoder and enter the x86 market.
>
> Seriously, could you stop trolling?
I am not trolling, and if someone defends the Renesas RX as a valid design choice instead of a wannabe then that would be a good thread.
The Renesas RX has byte at a time instructions, string instructions which means microcode overhead, and heaven forbid ADD from memory. The hardware guys moan about ADD from memory, actually they moan about all three, it's why everyone else is RISC.
The only upside is good code density, but it comes at hardware cost and design pain, of course transistors are cheap today, but design is not.
Renesas was not going to get any traction being late to the game with just another RISC chip, maybe this retro design makes sense for all the different 8 bit families that Renesas wants to upgrade to this design.
> > As the Renesas RX family expands up the performance ramp I fully expect Renesas to drop in
> > a x86 decoder and enter the x86 market.
>
> Seriously, could you stop trolling?
I am not trolling, and if someone defends the Renesas RX as a valid design choice instead of a wannabe then that would be a good thread.
The Renesas RX has byte at a time instructions, string instructions which means microcode overhead, and heaven forbid ADD from memory. The hardware guys moan about ADD from memory, actually they moan about all three, it's why everyone else is RISC.
The only upside is good code density, but it comes at hardware cost and design pain, of course transistors are cheap today, but design is not.
Renesas was not going to get any traction being late to the game with just another RISC chip, maybe this retro design makes sense for all the different 8 bit families that Renesas wants to upgrade to this design.