Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on September 23, 2013 10:24 am wrote:
> Patrick Chase (patrickjchase.delete@this.gmail.com) on September 23, 2013 10:17 am wrote:
> > POWER8 is reported to have a 64KB, 2 cycle L1 at 4 GHz.
> >
> > The 180 and 130 nm P4 variants had 2-cycle L1s at up to 3 GHz all the
> > way back in 2003 or so(though admittedly quite a bit smaller at 8 KB)
>
> All those processors were designed for a very different power-budget; some of the
> compromises they made to achieve that L1 latency might be completely unsuitable for a
> battery-powered CPU.

As I said a couple messages back, I think that we'll ultimately discover that it's a low-frequency design with a short pipeline. My point isn't that I think 3 GHz is likely, only that we don't know enough yet to rule it out.

With that said, a 3-clock L1 latency at 3 GHz may not be as expensive as you think.

The P4 was a decade ago, so that's not a valid comparison. Things that took obscene amounts of power then are easy now. POWER8 is current, so that's more interesting. Its wall-clock load-to-use latency is 0.5 nsec (2 clocks at 4 GHz).

Even if Cyclone could clock at 3 GHz, that only leads to a wall-clock load-to-use latency of 1 nsec. If they used the same microarchitectural approach as IBM (way prediction), then relaxing the latency constraint by 2X should reduce the power requirement by close to an order of magnitude.

You really can't rule it out at this point, which is my entire point.