Megol (golem960.delete@this.gmail.c) on September 27, 2013 11:02 am wrote:
> bakaneko (nyan.delete@this.hyan.wan) on September 26, 2013 3:06 pm wrote:
> > What I don't get is how Intel got the idea
> > that building Itanium would be successful.
> >
> > I'm reading through the wikipedia entry
> > for i860, which Intel worked on half a
> > decade earlier, and it is VLIW and it had
> > the same negative downsides from shoving
> > prediction into the compiler..
> >
> > So why did Intel think Itanium was going
> > to be any different?
>
> Because it was fundamentally completely different? The i860 was an exposed pipeline design,

I don't remember, was i860 exposed-pipeline only in dual-issue mode or in single-issue mode as well?

> the Itanium
> isn't. The Itanium was designed for backwards software compatibility which the i860 wasn't.

Well, branch delay slot in early RISCs was not designed for backward compatibility either. Which didn't prevent later higher-performance implementations from being backward-compatible.

>The i860
> supported superscalar execution - two instructions per clock which isn't VLIW in any traditional use
> of the word. As Itanium doesn't have exposed execution hardware it isn't really a VLIW either.

Yes, I really don't understand while many people, including Paul DeMone, consider i860 and IPF to be similar.