David Kanter (dkanter.delete@this.realworldtech.com) on September 30, 2013 1:41 pm wrote:
> Mark Roulo (nothanks.delete@this.xxx.com) on September 30, 2013 10:50 am wrote:
> > hobold (hobold.delete@this.vectorizer.org) on September 30, 2013 3:00 am wrote:
> > > David Kanter (dkanter.delete@this.realworldtech.com) on September 29, 2013 11:39 am wrote:
> > > [...]
> > > > That being said, I think the move from 28nm to 20nm or 16nm will be very tricky
> > > > because the process technology won't be as much help as everyone thinks.
> > > >
> > >
> > > It seems to me that the end of Moore's Law is something that no one wanted to
> > > see coming, but everybody will say "I told you so" as soon as we're beyond.
> > >
> > > IMHO the benefits of Moore's Law will end quite a bit before transistors stop shrinking.
> > > In the good ole' days, a shrink of structure size gave us three nice consequences:
> > >
> > > 1. lower energy consumption
> > > 2. higher switching speeds
> > > 3. lower cost
> > >
> > > Back when Pentium 4 was the first major CPU to be made in 90nm, the first
> > > of those three consequences started to vanish. (It seems to me the lion's
> > > share of design efforts these days is focused on compensating for this.)
> > >
> > > Today, number two on the list is on its way out.
> > >
> > > Number three will be next. I suspect that the difficulties and
> > > cost of moving to 450mm wafer size is foreshadowing this.
> >
> > There is some evidence that #3 is on the way out for everyone but Intel.
> >
> >

> > "28nm is the first process shrink which doesn’t deliver
> > a cheaper chip, says Scott McGregor, CEO of Broadcom.
> >
> > According to McGregor, not only is 28nm more expensive than 40nm now, as might be
> > expected at the start of a node, but that, on Broadcom’s current projections,
> > 28nm will never be cheaper than 40nm across the whole lifetime of the node."
> >
> > http://www.electronicsweekly.com/mannerisms/manufacturing/the-end-of-the-learning-curve-2012-05/
> >

> >
> > and:
> >
> >
> >
> > Interestingly, Intel claims that they are still seeing cost advantages to scaling:
> >
> >

> > Projections from an IMEC keynote that 14-nm wafers will be 90 percent more expensive
> > than 28-nm parts due to the lack of EUV lithography are inaccurate, Bohr asserted.
> > The cost increase for 14-nm wafers at Intel 'is nowhere near that,' he said.
> >
> > 'Cost per wafer has always gone up marginally each generation, somewhat more so in
> > recent generations, but that’s more than offset by increases in transistor density
> > so that the cost per transistor continues to go down at 14 nm, Bohr said.
> >
> > http://www.eetimes.com/document.asp?doc_id=1262877
> >

> >
>
> Some of this is just customers squawking about TSMC's pricing. The optimal strategy for
> TSMC is to charge as much as they can for a new process to get all the customers with a
> high willingness to pay and gradually lower pricing to expand the customer base. So some
> of the complaints are just customers trying to negotiate in the public arena with TSMC.
>
> However, what is different now is that foundries need to use double patterning on metal layers
> (as an aside, I'm not sure when they first used DP for transistors), which is definitely painful
> for throughput/cost. That drives cost up, which in turn drives wafer pricing up.
>
> Intel's approach to metallization is much more cost effective, but
> means more restrictive design rules and a bit of a hit on density.
>
> David
>

There are several schemes for double patterning, cut masks, which Intel has been using for poly since 45 nm. (That's why they were able to skip immersion lithography at the 45 nm node.) There, you one mask to pattern a 1D grating. You then use one (or more, depending on cut pitch) masks to cut the grating to make your desired layout. This obviously requires your physical design to be 1 dimensional for a given layer. I believe the foundries have started requiring 1D poly at 28 nm. (I may be mistaken here though.) Using immersion lithography, this technique is limited to 80 nm pitch. (2D patterns are limited to 120 or 130 nm pitch, I think...). Even though this technique requires the use of multiple masks and multiple litho and etch steps this is not typically considered double patterning by most folks because the double patterning aspects of the technique are hidden in the restrictive design rules.

Then there is self-aligned double patterning (aka spacer double patterning), a sort of extension of line and cut mask patterning, where spacers are deposited on a grating created with standard lithography. Here, the reduction in pitch does not depend on an additional lithography step. Intel uses this extensively. It's also used extensively in memory. They're using it for fin creation with their 22 nm process and based on their use of gridded design rules for 80 nm metal pitch at 22 nm, will likely do something similar with SADP metal layers for 14 nm. It's also relatively extendable to smaller pitches by further pitch division via additional spacer deposition and etch steps.

The foundries are using litho-etch-litho-etch for double patterning of metal layers at 20 nm. This requires knowledge of "colorization" for your physical design of the metal layers. i.e, you need to do your physical design while aware of the fact that the layout needs to be split into two masks. It also becomes less extendable due to the fact that each further reduction in pitch requires an additional litho and etch step which are the two most expensive pieces of equipment in the fab. In order to switch to an Intel style patterning scheme it would require significant investment in porting a ton of physical IP to gridded design rules and is probably only relatively simple for FPGA manufacturers. This is also likely why we still don't see internally fabricated Intel wireless modems.