RichardC (tich.delete@this.pobox.com) on September 30, 2013 11:13 am wrote:
> Kevin G (kevin.delete@this.cubitdesigns.com) on September 30, 2013 10:53 am wrote:
>
> > One oddity in Intel's announcements is that they plan on
> > having three 14 nm plants. Intel only has two 22 nm
> > plants and they were claiming excess 22 nm capacity. That
> > leaves me scratching my head as how they expect to
> > maintain capacity with three 14 nm plants, one of which is
> > 450 mm wafer based. Intel's plans call for more mobile
> > devices which 14 nm production will be key, but that wouldn't make up the increased volume would it?
>
> I wonder whether we're looking at the mobile stuff the wrong way. Intel's old business
> model was to make the cpu's on the bleeding-edge process, and then keep the older fabs
> busy with chipsets and other stuff. But that got tricky once most of the chipset (and GPU)
> migrated onto the CPU die. I wonder whether their real goal is still to keep the
> bleeding-edge fabs for high-margin cpu's (with more and more cores and bigger GPU's
> and other integrated stuff), and use relatively low-margin tablet/smartphone SoCs
> to keep generating revenue from the older fabs. 22nm fabs aren't chopped liver, when
> a lot of the competition is at 28, 32, and even 45nm.

Intel used to have their north bridge chips on an N-1 process and south bridge on an N-2. When the north bridge was initially integrated in the Nehalem generation, the south bridge was still N-2. Haswell changed things and moved to an N-1 south bridge to reduce power consumption of the platform further. Current indications point toward Broadwell's south bridge at N-1 process: 22 nm.

Another factor that has changed over the years is that Intel has become the sole supplier of chip sets. The last generation that had this luxury was Core 2 on the desktop and the Diamondvile for the Atom line. This partially offset the change brought on by integrating the north bridge into the CPU die.

A Skylake SoC will have no need for a south bridge. This would relieve pressure on the 22 nm process. The area demand for 22 nm Z97 chipsets + 14 nm Broadwell will be larger than Skylake SoC on 14 nm due to the chipset shrink. This still doesn't account for the doubling of capacity that a 450 mm wafer, 14 nm process fab brings.

Intel's E, EP and EX lines will also be moving to 14 nm over time but they're significantly lower volume than Intel's x86 lines for mobile/laptop/desktop. The N-2 strategy for chipsets is still in play here as the power consumption here isn't as critical. The number of chipsets to CPU sales isn't 1:1 as there are dual and quad CPU socket systems. However, the move to DDR4 in these areas allows Intel to re-introduce memory buffers. These will likely be manufactured on N-2 or N-1 nodes. I can see Intel doing what IBM has done and put L4 cache into the memory buffers which would increase further increases demand but again, on N-2 or N-1 processes.

Intel is using additional dies for an optional 22nm based L4 eDRAM cache on Haswell. Broadwell is all set to use the same die for its optional L4 eDRAM cache, thus making it an N-1 for that generation instead of just N. The real question is if Skylake will use the same eDRAM die for L4 cache or utilize a new 14 nm based design. Considering that the L4 cache will likely remain optional for Skylake, it wouldn't account for the 14 nm volume deficit.

Intel's other product lines like Ethernet controllers etc., will remain several nodes behind their cutting edge CPU process.

The only thing that'd make sense for Intel to justify the number of 14 nm fabs would be them being aggressive on the foundry front.