Purana Archer (ancientarcher.delete@this.gmail.com) on October 2, 2013 12:26 am wrote:
> mas (a.delete@this.b.com) on October 1, 2013 4:46 pm wrote:
>
> > No. The foundries for better or worse have decided to do hybrid FinFET technology where the layout back-end
> > is one size bigger so 14-16nm FinFETS are allied to a 20nm back-end and 10nm FinFETs are allied to 14-16nm
> > back-ends etc. Intel will be the first to a genuine 10nm shipping
> > in 2016 and 7nm probably too in 2018. Multiple-patterning
> > cost is the killer holding the foundry layout back-end at
> > 20nm which already uses expensive double-patterning.
> > It may take EUV or an equivalent for the foundries to get to 14nm layout and 7-10nm layout is just too far
> > technically for you to make a bold claim as you have about beating Intel.
> >
>
> Metal pitch width has nothing to do with performance but with density. Currently, Intel has a higher metal
> pitch width of 80nm (versus node size of 22nm), larger than either TSMC or Samsung at 64nm (vs node size
> at 28nm). When Intel moves to the smaller metal pitch width of 56nm in its 14nm node size, it will have
> a smaller metal pitch width than either TSMC or Samsung, which will retain the 64nm metal pitch width.
> Just as the larger pitch width of Intel doesn't confer upon it a performance disadvantage currently, the
> smaller pitch width of Intel in the next couple of years, won't give it a performance advantage.
>
> On the 10nm, TSMC and Samsung WONT be carrying over the pitch width from the 14/16nm. At every node until now,
> they have been better than Intel (except the 14/16nm node) and I expect that to continue for the 10nm.
>
> > So in conclusion I don't know whether capex spending is that a great indicator of
> > future success. Your capex/process spending also has to be smart, efficient and innovative.
>
> If capex spending is not, then what is? What, you think Intel employees shit
> gold and fart jasmine?? If you have monopoly on something that is a different
> story, but thats not the case here. Otherwise, it's all about spend.
>
> > FWIW Digitimes is reporting the initial 20nm yields are not good ...
> >
> > digitimes.com/news/a20130923PD215.html
> >
> > 'The current yield rate of Samsung's 20nm is estimated to be as low as 10%, the sources noted.
> > At TSMC, its 20nm facilities are operating at 20-30% yield rates, the sources said.'
>
> Current 20nm yields are low, doesn't mean anything.
>
>
>
>
>


You're sounding a lot like the foundry apologists who comment on EETimes.

First of all, metal pitch at 28 nm is not 64 nm (95 nm is their minimum metal pitch for 28 nm), they only reach 64 nm metal pitch at 20 nm. This will be carried over to the 16 nm node. At 14 nm, Intel will almost definitely be below that (there's no published info, but my guess is 56 nm), likely resulting in both density and performance advantages (almost entirely dependent on process implementation since 65 nm) when compared to foundries, something they haven't had at equivalently named nodes for 5 or 6 years, indicating that they will

And yeah, if you've worked in any kind of semiconductor process development you'd know that Intel is very different from other folks in how technology development works there. People actually do matter; it's not just a matter of how much money you throw at the problem.