Anonym (anon.delete@this.nym.com) on October 2, 2013 1:37 pm wrote:
> TSMC Capex and Intel Capex aren't comparable numbers. Intel's tool reuse rates between nodes
> are north of 80%, perhaps over 90%. Foundry's are much lower -- and even then reuse only happens
> when the foundry thinks there is too much mature node capacity. Which is rare.
>
> Furthermore, foundry yields are lower so they need more equipment per good die out. Finally, as tarlinian
> has pointed out, Intel's likely adoption of BEOL SADP and gridded design rules at 14nm means sigficantlt
> less litho equipment, which means a much cheaper fab per unit of leading edge capacity.
>
> I'll bet you $10B in TSMC Capex at 20nm would result in same die output or less as $5B
> in Intel Capex.
>
>
> Purana Archer (ancientarcher.delete@this.gmail.com) on October 2, 2013 12:09 am wrote:
> > David Kanter (dkanter.delete@this.realworldtech.com) on October 1, 2013 9:06 am wrote:
> > > Purana Archer (ancientarcher.delete@this.gmail.com) on October 1, 2013 5:52 am wrote:
> > >
> > > > all of you are assuming that the ARM fab ecosystem is making losses after selling such
> > > > cheap silicon. not true at all. TSMC and Samsung foundry are still making money.
> > >
> > > > As for capex, Intel will spend $11bn in 2013 with $2bn reserved
> > > > for 450mm trial (not >production, just trial).
> > >
> > > > TSMC will spend $10.5bn and Samsung $7-8bn. GloFo will spend $5bn.
> > >
> > > You realize that Samsung spends most of its capex on DRAM and NAND, right? Moreover, most
> > > of these folks are just spending money to replicate work that Intel has already done.
> > >
> >
> > I was not talking about Samsung's total capex, just the capex on Logic which is expected to be around
> > US$7-8bn. Samsung's total capex for 2013 is expected to come at US$23bn (far far higher than that
> > Intel) includes its capex on DRAM, NAND, consumer electronics and displays. On just the logic capex,
> > the point I was making was that this is the first time in 25 years, since the start of the microprocessor
> > industry really, that a competitor in Logic is able to match Intel's capex. That has huge implications.
> > Assuming the other guys ,like Samsung, TSMC and GloFo are not entirely stupid and don't literally
> > piss away the money, you are going to see a narrowing of the tech lead that Intel enjoys today -
> > which is the direct result of its outsized capex spend of previous years.
> >
> > > > The ARM ecosystem spends significantly
> > > > more and all these players are making money.
> > >
> > > Global foundries isn't making money. TI already bailed from the
> > > mobile market. It's not clear that it's that good of a market.
> > >
> >
> > Yes, GloFo is not making money. Not to say that it wont. But yes, it is investing
> > so that it can remain relevant vs its competitors (meaning TSMC, Samsung).
> >
> > > >Just look at TSMC's P&L. So what is the outlook for Intel's
> > > > edge in process node? How long will it sustain with these guys bearing down on it at such >a rate...
> > >
> > > Why don't you tell us? Right now, Intel is 1.5-2 years ahead of everyone else in terms
> > > of moving to the next node, and 3-4 years ahead in terms of performance enhancements (e.g.,
> > > strained silicon, HKMG, FinFETs, etc.). When do you expect that gap to narrow?
> > >
> > > David
> > >
> >
> > Well, Intel introduced HKMG in 2007, Samsung in 2012 and
> > TSMC in 2013. Finfet - Intel introduced in 2011 and
> > TSMC and Samsung in 2014. So, the gap is already narrowing. My point is, if you don't assume the others are
> > chipmunks, they will invest the capex spend relatively wisely, then there is no way that Intel can maintain
> > that 3-4 years edge in tech when spending the same or less.
> > It is mathematical really, the edge is a function
> > of the cumulative capex and r&d spend. when the spend gap narrows, the tech difference should also narrow.
> >
>
>

While I appreciate your response, I hate to see top-posting invade forums. To be fair, one could argue that the typical density advantages for foundries due to 2D design rules (which I think can be overcome by clever enough layout) and more aggressive litho w.r.t. other node features makes the die smaller, allowing for smaller good wafer area output to produce more functioning products.