> > > The only thing that'd make sense for Intel to justify the number of
> > > 14 nm fabs would be them being aggressive on the foundry front.
> >
> > There are not going to be an 450 mm 14 nm fabs. 450 mm production
> > is not happening for at least 4 years; I'd guess on the 7 nm node.
>
> Intel does have 450 mm wafer production capabilities set for a 2015 introduction.
> http://www.techpowerup.com/179065/intel-shows-off-industrys-first-fully-patterned-450-mm-wafer.html
> http://www.tomshardware.co.uk/intel-fab42-14nm-cpu-factory,news-37599.html
>
> From all indications, a 450 nm wafer line is going to be the last node to come online.
> Thus all Broadwell launch chips will be off of their 300 mm wafer lines.

From an EETimes article:

"Back in October 2012 Intel said construction of D1X module 2 would begin in 2013 and take more than two years to complete, with wafer manufacturing equipment installation expected to begin in 2015, which would put first wafers out in 2016.

...

but there is no schedule for when the fab will start, the [Intel] spokesperson added.

"We have not said when it will come online because we have not said when we expect to have 450mm wafer production. Nor have we forecast a process node for 450mm," the spokesperson said in email to EE Times."

Intel is building out a 450mm capable building, but actual start up may be more complicated, because it depends on tool readiness.

For example, I am not sure how ASML is doing their EUV R&D. I'm assuming they are all working on 300mm wafers right now, but I know that Intel and others paid them to kickstart the 450mm work.

It's also not clear how Intel will handle EUV insertion. They could do a mid-node insertion, but that would not necessarily result in big advantages.

I haven't really thought about how that would work. I would think that at the same node, EUV should enable fewer design rules and/or higher throughput (by eliminating multi-patterning steps). But the real question is whether Intel wants to redo all their IP on a given node to take full advantage of EUV (i.e. looser design rules). That sounds like a lot of work, so I'd expect initially they use it to only boost throughput.

But perhaps someone that knows more about fab equipment than me can add something to this discussion (paging tarlinian or Mark?).

David