Tarlinian I'm curious, what do you think Intel's technology roadmap by node looks like? What do you think the major features of 14nm, 10nm, and 7nm will look like?

when/if do you think we'll see

TSVs?
Quantum Wells?
III-Vs?
metallic source/drain?
vertical device orientation?
optical BEOL layer?
graphene/dichalcogenide channels
sequential 3D device integration?

My bets:

14nm -- high AR fins with tight pitches (40nm); 60nm M1,M2,M3 pitches;poly pitch is 60nm
10nm -- SiGe quantum wells; TSVs
7nm -- Ge quantum wells with GAA structure / perhaps InGaAs NMOS channels; vertical device orientation; perhaps metallic source/drain...
5nm -- III-V NMOS QW channels; Metallic S/D; III-V TFETs and NEMS relays for some circuitry; sequential 3D integration with PMOS over NMOS

tarlinian (tarlinian.delete@this.gmail.com) on October 4, 2013 12:23 pm wrote:
> David Kanter (dkanter.delete@this.realworldtech.com) on October 4, 2013 11:24 am wrote:
> > > > > The only thing that'd make sense for Intel to justify the number of
> > > > > 14 nm fabs would be them being aggressive on the foundry front.
> > > >
> > > > There are not going to be an 450 mm 14 nm fabs. 450 mm production
> > > > is not happening for at least 4 years; I'd guess on the 7 nm node.
> > >
> > > Intel does have 450 mm wafer production capabilities set for a 2015 introduction.
> > > http://www.techpowerup.com/179065/intel-shows-off-industrys-first-fully-patterned-450-mm-wafer.html
> > > http://www.tomshardware.co.uk/intel-fab42-14nm-cpu-factory,news-37599.html
> > >
> > > From all indications, a 450 nm wafer line is going to be the last node to come online.
> > > Thus all Broadwell launch chips will be off of their 300 mm wafer lines.
> >
> > From an EETimes article:
> >
> > "Back in October 2012 Intel said construction of D1X module 2 would begin in 2013
> > and take more than two years to complete, with wafer manufacturing equipment installation
> > expected to begin in 2015, which would put first wafers out in 2016.
> >
> > ...
> >
> > but there is no schedule for when the fab will start, the [Intel] spokesperson added.
> >
> > "We have not said when it will come online because we have
> > not said when we expect to have 450mm wafer production.
> > Nor have we forecast a process node for 450mm," the spokesperson said in email to EE Times."
> >
> > Intel is building out a 450mm capable building, but actual start up
> > may be more complicated, because it depends on tool readiness.
> >
> > For example, I am not sure how ASML is doing their EUV R&D. I'm assuming they are all working on
> > 300mm wafers right now, but I know that Intel and others paid them to kickstart the 450mm work.
> >
> > It's also not clear how Intel will handle EUV insertion. They could do a mid-node
> > insertion, but that would not necessarily result in big advantages.
> >
> > I haven't really thought about how that would work. I would think that at the same node, EUV should enable
> > fewer design rules and/or higher throughput (by eliminating multi-patterning steps). But the real question
> > is whether Intel wants to redo all their IP on a given node
> > to take full advantage of EUV (i.e. looser design
> > rules). That sounds like a lot of work, so I'd expect initially they use it to only boost throughput.
> >
> > But perhaps someone that knows more about fab equipment than me can
> > add something to this discussion (paging tarlinian or Mark?).
> >
> > David
>
> I think EUV will come in earliest for Intel at 7 nm, which is most likely to be shared between 300 mm and 450
> mm as well. They've already publicly said it will miss 10 nm. (Intel did a shared 200/300mm node when that
> handover occurred also.) I also think at that point EUV will require multi-patterning anyway. (I think the
> minimum bi-directional metal pitch for current relatively low NA EUV scanners is 56 nm; high NA EUV will require
> larger masks and no one can even make current EUV mask blanks economically; forget even bigger ones.) I think
> the main benefit of EUV will be cost of tool/process related since it will allow you to skip additional litho
> and etch steps. It also makes the process more robust since less multi-patterning (even Intel style gridded
> design rule pitch splitting based MP) requires extremely precise overlay. At those tight dimensions I've heard
> that the overlay budget will be matter of making a better scanner; there are other issues that come into play.) Essentially current multi-patterning
> schemes eventually becomes technically unfeasible due to overlay problems, at which point EUV becomes a requirement.
> (I have heard a few techniques that can help postpone this problem some more, but they are rather exotic. Then
> again, Intel has always been the master of exotic, so you never know.)