Anonym (Anon.delete@this.nym.com) on October 4, 2013 11:39 pm wrote:
> Tarlinian I'm curious, what do you think Intel's technology roadmap by node looks
> like? What do you think the major features of 14nm, 10nm, and 7nm will look like?
>
> when/if do you think we'll see
>
> TSVs?
> Quantum Wells?
> III-Vs?
> metallic source/drain?
> vertical device orientation?
> optical BEOL layer?
> graphene/dichalcogenide channels
> sequential 3D device integration?
>
> My bets:
>
> 14nm -- high AR fins with tight pitches (40nm); 60nm M1,M2,M3 pitches;poly pitch is 60nm
> 10nm -- SiGe quantum wells; TSVs
> 7nm -- Ge quantum wells with GAA structure / perhaps InGaAs NMOS channels;
> vertical device orientation; perhaps metallic source/drain...
> 5nm -- III-V NMOS QW channels; Metallic S/D; III-V TFETs and NEMS relays
> for some circuitry; sequential 3D integration with PMOS over NMOS


I don't think Intel even know yet what 5 nm is going to be yet.

Your 14 nm predictions seem like a reasonable guess. My guess is that metal layers will be minimum pitch SADP off dry ArF litho, basically equivalent to current 22nm fin pitch.

For 10 nm, what I know I can't really say. I work at an equipment vendor so I have some idea of what features may or may not be getting added for 10 nm, but I can't disclose them for obvious reasons. (The stuff I say on here is based on publicly disclosed information.)

For 7 nm, I'd just be guessing. My personal opinion is that the TFET gives the best bang for the buck in terms of improved device characteristics. Speed has no chance of going up with the TFET. But RC delay is going to be so bad at that point, I doubt improving gate delay is going to help with speed improvements at that point. The other realistic options are gate all around structures, which would be vertically oriented, or III-V fins.
The TFET is very difficult due to extremely complicated epi processes for exotic materials in order to get a relatively high I_on (still much lower than CMOS though). GAA has all the inherent problems associated with CDs not being controlled by litho, but rather by etch and CMP. III-V channels are probably the least problematic, but still have issues with gate stacks, passivation, etc.