Daniel (x.delete@this.y.z) on November 19, 2013 3:28 am wrote:
> Eric (eric.kjellen.delete@this.gmail.com) on November 18, 2013 1:17 pm wrote:
> > David Kanter (dkanter.delete@this.realworldtech.com) on November 18, 2013 3:03 am wrote:
> > > Knights Landing is Intel’s first clean sheet redesign of the Larrabee family, targeted at throughput
> > > computing and manufactured on a 14nm process with products expected in late 2014 or early 2015.
> > > The adoption of AVX3, on-package embedded DRAM, and bootable products have been disclosed, but
> > > most details are unknown. This article analyzes the options available for the Knights Landing
> > > CPU core and explains why Intel’s existing cores are a poor fit for the target workloads, concluding
> > > that the most likely outcome is a new custom core for Knights Landing.
> > >
> > > http://www.realworldtech.com/knights-landing-cpu-speculation/
> > >
> > > Questions, comments and discussion are welcome!
> > >
> > > David
> >
> > Great article, about one my favorite areas in this field. I recalled another article I read where
> > some Intel executive stated that future versions of what would be Xeon Phi were going to be based
> > on Atom cores and I found one in The Register from 2011 where Justin Rattner does address this issue:
> > "But in the future, MIC will be based on Atom cores, and then the integer gap between Xeon and MIC
> > will start to close." http://www.theregister.co.uk/2011/09/15/intel_rattner_mic_coprocessor/
> >
> > So going by this and by what you said about Bonnell not having been productized (I don't know
> > if research silicon maybe has been fabbed though) on 22nm or 14nm, presumably upcoming Xeon
> > Phi generations have been developed in parallel with and in connection to development on the
> > future Atom cores (i.e. not Bonnell) and the KNC cores cores will be based on them, but as in
> > the case of the P54C derivative extended with a 512-bit vector unit and other adaptations.
>
> Heise (http://www.heise.de/newsticker/meldung/Intels-Supercomputer-Beschleuniger-Xeon-Phi-mit-72-Kernen-integriertem-InfiniBand-und-3-TFlops-DGEMM-2049668.html)
> claims KNL using 72 Cores based on an extended Silvermont architecture now featuring OoO FPUs. I wonder how reliable
> their Sources are, because ~3TF with just 72 Cores would result in (boost) clocks above 2.5GHz.

The way the numerics folks score flops, they treat a multiply-accumulate operation as two floating point instructions.

So ... single-precision (32-bit wide) instructions on the 512 wide vectors gives us 16 floats per clock.

72 cores x 16 floats x 2 ops/clock = 2,304 ops/clock for the entire chip.

1.3 GHz will get you to 3 TFLOP. 1.3 GHz is quite plausible.

Does anyone actually believe that the only instructions running will be single-precision multiply-accumulate? No, but this is a peak number, not something that normal people will see (also, you might get close to it if you are doing mostly matrix multiply).