Michael S (already5chosen.delete@this.yahoo.com) on November 21, 2013 6:48 am wrote:
> Eric (eric.kjellen.delete@this.gmail.com) on November 21, 2013 2:28 am wrote:
> > Daniel (x.delete@this.y.z) on November 20, 2013 2:04 pm wrote:
> > > Could they have opted for 2 vector units per core? This would make KNL more similar
> > > to SKL from an EU point of view and might explain the decision to go for OoO FP.
> >
> > That thought struck me too: 2x 512-bit vector units with FMA would give 32 DP FLOP/clock
> > and 72 cores would need 1.3 GHz to give 3 TFLOPS (3 TFLOP/s / (32 FLOP * 72) = 1.302 GHz)
> > which would be a more incremental clock frequency boost over previous-generation MIC.
>
> 2 FPUs on 2-issue core? That's silly. 2-issue is barely enough to keep one FPU reasonably busy. I say,
> barely, because, judging by Top500 list, KNC (and Kepler) delivers much lower sustained-to-peak ratio
> than just about everybody else, and that on the benchamark that is commonly considered easy.
>

Yeah, that explanation might not make sense. However, it has to be explained how 72 cores (presumably Atom/Silvermont) with a 512-bit vector unit (for 16 DP FLOP/cycle with FMA) can achieve 3 DP TFLOPS. My first thought would be that the number of cores is incorrect, but Intel has previously stated that future Xeon Phi designs (and this was said in 2011 and should include Knights Landing) will be based on Atom cores. And getting a comparable high number of cores (>100) that they would from a scale-up of the P54C derivative many-core design in KNC (57-61 cores) would probably not be possible if Atom cores are used, as one Atom core is much larger and power hungry.

What's puzzling is also that while 2.6 GHz is way too high for a highly-parallel chip, 72 cores that compute 16 DP FLOP per core and cycle at this clock frequency exactly matches the 3 DP TFLOPS peak performance figure provided by Intel, though this so far is not exactly significant as the 2.6 GHz was something we grabbed out of thin air for the very purpose of solving this equation. On the other hand, assuming 32 DP FLOP pe core and cycle and a matching halving of the clock speed then results in a 1.3 GHz clock frequency which is only slightly higher than Knights Corner (proudction Xeon Phi of this generation offers clock frequencies in a range from 1.053 GHz to 1.238 GHz) and a very realistic increase for the die shrink from 22nm to 14nm. This would suggest that the 72 core figure is correct but Intel has somehow managed to make each core work as if it had double 512-bit vector units or a single 1024-bit vector unit (here I am reminded of Nicholas Capen's predictions for future AVX/LRBni convergence) so that it can process 32 DP FLOP/cycle.