none (none.delete@this.none.com) on November 18, 2013 3:59 am wrote:
> Nice article as usual :-)
>
> Just one comment:
>
> "Moreover, the L1D in Knights Corner was 32KB and 8-way associative to work with 4
> threads – the 6 way associativity in Silvermont is simply insufficient and would cause
> excessive conflicts."
>
> My understanding is that Intel use 6/8 ways no because of MT but to prevent having to
> use hardware alias handling for 4KB pages.

I think that's correct - Every Intel x86 core from the 486 on has had a VIPT L1 D$, with set size less than or equal to the smallest x86 page size of 4 KB. For example, the Core2 did not have SMT but did have an 8-way L1 D$.

With that said, it doesn't really diminish or argue against David's point. Regardless of how Intel got to high associativity to begin with, they wouldn't want to back off on that attribute in such an aggressively multi-threaded core.