Michael S (already5chosen.delete@this.yahoo.com) on November 24, 2013 7:06 am wrote:
> Integer instructions are the smaller part of the problem. The bigger part are memory
> instructions.
> In my experience, for typical linear algebra algorithm with 32 sw visible registers
> it's pretty hard to reduce the number of memory accesses per to FMA below 0.7-0.8.
> And in that regard linear algebra is easier than most.

Agreed.

> I am not sure that Fermi/Kepler reference is relevant in discussion
> of KNL. I am sorry that I did it myself in a previous post.

Besides the instruction set and SIMT/SIMD differences, aren't they close architectures targeted at the same market?

> Certainly not for KNC-style core, where load and OP are separate pipeline operations.
> For Bonnel-style core, with its CISC (or, if you want, TI TMS320C30/C40 -style) load+op pipeline - may be.
> But resulting core wouldn't resemble Bonnel/Saltwell, even less so Silvermont.

I thought KNC was handling load+op in the same pipeline. If so I do not understand the distinction with Bonnel.

> > I am much more skeptical about out-of-order execution of a fully mask-predicated instruction set...
>
> You mean, too many register inputs per uOP?
> I didn't look at AVX-512 at sufficient details. How many register inputs will be needed per FMA?

More than the number of inputs, the problem is partial dependencies that prevent proper register renaming. Consider pseudo-code such as:
1: add r1{k1}, r0, r2
2: sub r1{k2}, r0, r3

If masks k1 and k2 have any chance of overlapping, then the result of instruction 2 depends on the result of instruction 1 (needs to read-modify-write r1).
A straightforward OoO implementation would assume a data-dependency and schedule instruction 2 once the result of instruction 1 is available. This is much worse than running in-order and merging during write-back.
Of course, in most cases k1 and k2 won't overlap (this is typically an if-then-else that went through if-conversion).

This is a similar issue as mixing AVX and SSE instructions, or 16-bit and 32-bit x86. Legacy instructions that only update the lower part of registers create partial dependencies. At least on Ivy Bridge, the retribution for forgetting a vzeroupper is a ~50-cycle penalty...
Except it gets much worse with masked instructions, since the register subset that an instruction updates is unknown at schedule time, instead of being nicely encoded in the instruction...

I am really curious to know how Skylake (or KNL if OoO) intend to handle this.
I guess the easiest way would be to crack every predicated instruction into 2 µops:
add tmp, r0, r2
merge r1, k1, r1, tmp
sub tmp, r0, r3
merge r1, k2, r1, tmp
But this is not so cheap, and merges still need to be done in-order.