Adam Kalisz (adam.kalisz.delete@this.outlook.com) on November 26, 2013 2:20 am wrote:
> Sorry, if I don't follow the commenting rules and English grammar right
> - it's my first comment here and English is my 3rd language.
> I wrote with David about Intel KL on Twitter.
>
> -->
>
> I guess, I was right about the DRAM on package, I wasn't right about the size of it though. It looks like,
> there will be 8 or 16GB of it instead of my initial guess of 1 GB (I thought of Crystalwell which would be
> about 8x 100GBps) it looks like they will choose MCDRAM and some lower bandwidth - higher-density parts. I'm
> not very experienced in this field from the technical and manufacturing/ decission-making point of view.

I would love to see an 8 GB eDRAM option, but I don't know how this works out.

Anand has the 128 MB CrystalWell die at 84 mm^2 (on a 22nm process).

8 GB is 64x that ... so 5,376 mm^2. Even if we get a perfect size benefit from 22->14 nm, we're still looking at over 2,000 mm^2 just for the eDRAM. That seems ... um ... large?

More ... Anand also claims that "Under load, operating at full bandwidth, the power usage is 3.5 - 4.5W" ... so 64 of these and we have ~200W just for the eDRAM. Sure, we'll see some power savings (maybe) because of 14nm, but ...

Anyone?