David Kanter (dkanter.delete@this.realworldtech.com) on January 4, 2014 10:58 am wrote:
> Nicolas Capens (nicolas.capens.delete@this.gmail.com) on January 4, 2014 5:43 am wrote:
> > David Kanter (dkanter.delete@this.realworldtech.com) on January 2, 2014 wrote:
> > > "AVX3 is a load-op instruction set that can source one operand from memory for each
> > > operation (typically assumed to be a fused multiply-add or FMA). This means that the
> > > KNL core must have a 512-bit (64B) wide load pipeline for each vector unit."
> >
> > That seems like a bit of a leap.
>
> Nope, it's solid analysis. I'm willing to wager $ that I'm correct here.

I'm not seeing said solid analysis. You're leaping from AVX3 being a load-op instruction set, to Knights Landing necessarily having two load ports. All other x86 arithmetic instructions can also have a load operand, so why does Silvermont not have two load ports, using the same reasoning?

I'm not saying Knights Landing can't have two load ports, there might be other reasons why it does. So I'm not betting on anything. I'm just pointing out that one 512-bit load port seems like a possibility as well. If you could elaborate on why it "must have" two load ports, that would be much appreciated.

> > Wouldn't it be possible for one unit to be able to have a memory
> > source operand and the other to be able to have a memory destination operand?
>
> It's also possible for that to happen with 2 LSUs.

Certainly. But what I meant was having *only* one pipeline capable of taking a memory source operand, and the other one being the only one capable of storing the result into memory. Based on typical load/store requirements (see for instance Eric's example above) it's very useful to be able to issue a load and a store each cycle, but two loads per cycle seems much less of a necessity.

> > AVX-512 has a
> > relatively high number of registers so there are few stack accesses. GPUs are also fine with
> > having low L/S bandwidth per FLOP because of this.
>
> GPUs can have 100-200 registers per thread. KNL can have 32.

Kepler can have up to 255 registers per thread, but only at 1/8 occupancy. At full occupancy, 31 registers are available. AVX-512 can have many more than 32 live temporaries (even more than 255), by using the stack. This comes at practically no cost as long as there are available load/store cycles, and only very gradually decreases performance beyond that. In contrast the GPU can suffer significantly from the lower occupancy. Some optimization manuals therefore advise to use local memory to lower register pressure...

Anyway, the conclusion is still the same. AVX-512 has a relatively high register count, which lowers the need to access stack memory and thus may be a factor in why Knights Landing might have only one load port.

> > Requiring only two AGUs and one load and
> > store port significantly simplifies things and keeps power consumption down, which might be
> > more important than ensuring there's never a cycle lost because of load port availability.
>
> KNL will only have two AGUs, but the configuration is unclear. It could
> be 2 LD/ST or 1 LD + 1 LD/ST. There is no way it will be 1 LD + 1 ST.

Why?