> If this forum had basic search engine, I'd dig out Eric Bron's post where he demonstrates
> similarly strange (although much less strange) icc code generation for SandyB/IvyB
> targets, where performance degradation vs. straight-forward code is small,

I have done quite extensive measurements and there isn't always performance degradations, depending on the case, the heuristic looks good overall but there is indeed some cases where it's a bad choice

now, all my tests were with AVX/AVX2 code on SNB/IVB/HSV *with 2 load ports*

the fact that the same heuristic is used for KNL may be due to one or more of the reasons below:
- there is 2 load ports per core on KNL
- the compiler isn't mature enough for AVX-512 code generation, it can uses all the 32+8 AVX-512 registers but is too conservative, using obsolete register pressure avoidance heuristics
- there is a small "L0D read cache"

> not my point. My point is - compiler never tries to make execution more power efficient.

this is my understanding too for current compilers, but power efficient code is one design goal of AVX-512 with the predication masks, compilers should take that into account even in the context of absolute performance: KNC has a per core turbo mode, this will be most probably also the case for KNL