Michael S (already5chosen.delete@this.yahoo.com) on January 7, 2014 10:42 am wrote:
> Maynard Handley (name99.delete@this.name99.org) on January 6, 2014 6:52 pm wrote:
> > Eric Bron (eric.bron.delete@this.zvisuel.privatefortest.com) on January 6, 2014 6:35 am wrote:
> > > I have to confess that I was too quick to post the previous versions, well optimized code for
> > > arrays will looks like (with far higher load port pressure than I was initially stating)
> > >
> > > .B3.3:: ; Preds .B3.1 .B3.3
> > > vaddpd zmm0, zmm0, ZMMWORD PTR [rcx+rax*8] ;56.11
> > > add rax, 8 ;53.25
> > > cmp rax, r9 ;53.19
> > > jl .B3.3 ; Prob 82% ;53.19
> > > vshuff32x4 zmm1, zmm0, zmm0, 238 ;58.12
> > > vaddpd zmm0, zmm1, zmm0 ;58.12
> > > vpermpd zmm2, zmm0, 78 ;58.12
> > > vaddpd zmm3, zmm0, zmm2 ;58.12
> > > vpermpd zmm4, zmm3, 177 ;58.12
> > > vaddpd zmm5, zmm3, zmm4 ;58.12
> > >
> > >
> >
> > So what I said.
> >
> > No-one cares about the cross lane crap at the end. The part that
> > matters is the loop, which is one load per vector FP op.
> > And this strikes me as the most common low-load pattern. Just as common would be
> > a dot product which would need two loads in the inner loop along with one FMAC.
> > I just don't see how you can claim that the DYNAMIC instruction
> > count is "commonly" less than one load per vector FP op.
>
> Hopefully, in intended workloads both dense matrix multiplication and convolution between long vector
> and short-but-not-very-short vector are more common then individual isolated dot product.
> DGEMM and CONV can have load to arithmetic vector op ratio significantly lower than one. Unfortunately, on
> AVX-512F ISA the reduction in load to arithmetic vector op ratio looks impossible without accompanying reduction
> in arithmetic vector op to total # of instructions ratio. The later is not a problem on uArchs like Skylake
> (assuming that Skylake inherits HSV arrangement of execution ports), but it will have significant negative
> impact on KNL, assuming that David is correct about two FMAC-capable VPUs per dual-issue core.
>

Look at what I said in my first post on this subject:
"
> Because typical code only requires one (unique) memory source operand
> every two instructions, especially when you have 32 registers.
>
Where does this claim come from? I'm not denying it, but it doesn't seem to match anything in my experience. Maybe very dense blocked matrix code (and FFTs, which are basically isomorphic to matrix code) but a simple reduction is going to want one load per FLOP, while anything more likely wants two loads per FLOP.
"
The claim (as I understand it) is that
(a) AVX512 is superfantastic because it can run well all sorts of general purpose FP code, unlike GPUs which (supposedly) basically fall apart for much more than matrix multiplication (and perhaps massive monte carlo)
(b) this typical "most" code has the 'requires one (unique) memory source operand every two instructions'.

I don't believe these two claims are compatible. If (b) is true, then that 'most code' is probably all matrix multiplication, in which case it's already well served by GPUs.