Nicolas Capens (nicolas.capens.delete@this.gmail.com) on January 7, 2014 10:52 pm wrote:
> Michael S (already5chosen.delete@this.yahoo.com) on January 7, 2014 3:41 pm wrote:
> > Nicolas Capens (nicolas.capens.delete@this.gmail.com) on January 7, 2014 12:36 pm wrote:
> > >
> > > It's 18 loads for ~59 instructions. So you're perfectly fine with
> > > one load port to sustain an IPC of 2, like most workloads.
> >
> > We are not on the same wave, sorry. I don't even understand whether you are talking abot Skylake or KNL.
>
> I'm still talking about KNL (arguing that David's article should consider
> a single L1 load port as a possibility). I never brought up Skylake.
>
> > My point is, my excerpt above is half-reasonable on something like Skylake*, but if you will try
> > to run something of that style on KNL it will absolutely horribly suck, achieving, in ideal case
> > of 100% L1D hit rate, about 40% of peak theoretical FLOPs, and probably only 30% in real life. So,
> > for KNL, one has to use completely different coding style with much much higher load-to-FMAC ratio
> > and probably with heavy reliance on load+op with embedded broadcast form of FMA instruction.
>
> You should theoretically be able to achieve 60% peak theoretical FLOPs for this code on KNL (if it's based
> on Silvermont and has two vector units). I didn't notice before that 7 out of 8 of the "col += M;" can be
> folded into the loads. Anyway, it doesn't change the conclusion that one load port for L1 would suffice.

Are you sure in your arithmetic?
My original code contains 77 instructions. With transposed right-side matrix we can reduce it to 70 instructions. But if Eric is correct about slowness of 3-input permutes, then we have to add 8 more VSHUFF64x2 instructions for a total of 78.
Even taking the best case of 70 instructions, 32/70=45.7%, far away from 60%.