NoSpammer (no.delete@this.spam.com) on January 9, 2014 12:55 pm wrote:
> Nicolas Capens (nicolas.capens.delete@this.gmail.com) on January 9, 2014 12:40 am wrote:
> > It is not an easy assumption at all to consider this a compiler bug. Looking at ICC and Intel's
> > contributions to LLVM, their compiler engineers are exceptionally skilled. They would not ship
> > a compile with this behavior, unless it was intentional. So it's easier to look for other explanations,
> > such as the existence of a structure to provide duplicate memory operands.
>
> IMO it's easier to assume it is a compiler feature minimizing number of instructions, number of
> registers used, and length of dependency chain while not oversubscribing execution resources.

According to [1] an instruction with a memory operand consumes 40% more power. Since Xeon Phi is intended to compete with GPUs in the exascale race, it is unacceptable to read the same data from memory lots of times [2] versus adding one vmovaps instruction. The compiler didn't do this before, despite the fact that AVX-512F is barely any different from KNC's 512-bit ISA extension. They made a deliberate change, and one of the explanations for making sense out of it is that on KNL it's cheap to reuse recently loaded data, which implies the existance of an L0 cache.

I'm not saying this has to be the case. I'm just saying it might be a possibility and David's article shouldn't assume two L1 read ports to be a given, especially not based on x86 being a load-op ISA alone.

[1] http://www.eecs.harvard.edu/~shao/papers/shao2013-islped.pdf
[2] http://www.realworldtech.com/forum/?threadid=138897&curpostid=139173