Nicolas Capens (nicolas.capens.delete@this.gmail.com) on January 11, 2014 12:24 am wrote:
> And knowing how much an L1 access cost in power, that doesn't make sense unless they have
> 'something' to make it cheap for very locally reused data. I call that something an L0 cache.

This is an argument that really works against your thesis: memory accesses cost power, you suggest adding another dual-ported structure that needs to be wired to the L1, to the instruction fetch logic, reorder buffer, LSU and to the store-queue. That 'something' sits squarely in the middle of one of some of the most timing-critical paths in a processor and will be continuously burning power whether you use it or not. How do you possibly thing that's going to save power?

> The Intel compiler has been around for a long time, and AVX-512 is a very minor variation on KNC's
> 512-bit ISA extension.

Have you ever seen the output of the KNC compiler? I haven't and I'd be glad if someone would post it here.

> Also as someone pointed out elsewhere you need a somewhat representative
> compiler to generate traces that can be used during the design of the new architecture.

Very true however in my personal experience those compilers are never shared with the public.

> And lastly
> this behavior isn't coming from some complicated experimental optimization. This is part of basic
> register allocation and for decades the overall goal has been to minimize the number of memory operands.

That's just wrong: deciding what instructions to use happens during instruction selection, not register allocation, and in most compilers that happens *before* register allocation because the latter depends on the former (and it's also a highly compiler-dependent process). The two phases are not completely independent anyway as there's heuristics usually involved (to reduce register pressure, optimize for instruction decoding, etc...). On a new target those heuristics can easily yield wrong results resulting in poor code. Note that the heuristics driving instruction selection are not generic and usually depend on the machine description, so a very mature compiler with a brand new immature MD for a new core can still spit out some terrible code.

> To suddenly see that basic rule reversed cannot possibly be something Intel has overlooked.

Bugs happen and do so far more often than weird, never-seen-before microarchitectural changes appearing.

> There's a difference between it being the wrong solution and two L1 read ports being the right
> solution. The L0 cache is just one way Intel might avoid a 40% increase in power consumption,
> but the most likely one I've been able to come up with so far based on the compiler output.
> That you think that output is "probably" the result of an immature compiler, which it clearly
> isn't, is a much more interesting expression of doubt. So what's your other explanation?

The more this debate evolves and the more I'm keen on Michael S' thesis that there's really only one vector unit and L/S pipeline per core and there's twice as many cores as everybody expects.