Nicolas Capens (nicolas.capens.delete@this.gmail.com) on January 20, 2014 2:49 pm wrote:
> anon (anon.delete@this.anon.com) on January 20, 2014 1:19 am wrote:
> > > > If this is still not enough, I would say something which is much better thought-out in terms of
> > > > indexing and invalidation would be superior to this L0 idea, e.g., Intel's "signature buffer".
> > > >
> > > > http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.78.601&rep=rep1&type=pdf
> > >
> > > How is that superior? It's the exact same idea!
> >
> > No it isn't. There are similarities, but the actual details are much more extensive...
>
> Well, duh!

Err, yeah. Duh yourself. It is a better idea than the L0, because it has much better indexing and invalidation in my opinion. I don't know what is difficult about this concept for you.

It's a complete research paper. We're merely speculating about KNL here, for which
> back-of-an envelope ideas suffice to consider something viable or not. The 'signature buffer'
> also started as a back-of-an-envelope idea, for which you don't need the full details for
> it to make sense. So as a concept that doesn't make one superior to the other.
>
> Note that I'm not claiming KNL to have an L0 cache as described at all. I'm just proposing
> it as one possible way it may not require two L1 load ports.

You said it was the best possible way. That it was more power efficient, that complexity would not be an issue, etc etc.

> If you agree that as a conceptual
> idea it's worth exploring, or there could be variants that reduce the L1 load port needs,
> that's all I'm looking for. No need to turn this into another research paper.

Not only is there no need, there is no capability.

>
> > and
> > better thought out in the signature buffer. Indexing and invalidation, particularly.
>
> Which part of my indexing an invalidation explanation do you not understand?

I understood it, I said it was inferior to the signature buffer.

> It's a fully
> associative cache, but with just a couple entries per thread the indexing is extremely
> cheap. The index itself is basically the SIB encoding and part of the displacement.

"Basically", but not. Did you understand how the signature buffer works?

>
> For invalidation you track any writes to the base and index GPRs, and you track
> any L1 changes to the line corresponding to the entry. That's basically it.
> Any further details are insignificant for the viability of this concept.
>
> > And after all that, you still didn't answer any questions or show any calculations that
> > would justify your assertions that the L0 cache is the best possible thing imaginable.
>
> I answered all your questions. Also read the papers that I linked to. They give you all the calculations you
> need to determine whether an L0 cache could be viable. Let me know if there's anything significant I've missed
> that could change the equation. And again, I'm not claiming the L0 cache to be the best thing imaginable. I
> am merely questioning David's assertion that KNL needs two L1 load ports just because x86 is a load-op ISA.

The papers had nothing to do with what you propose, they were things like power savings of a line buffer, which is very different to what you're talking about.