Article: Knights Landing Details
By: Stubabe (Stubabe.delete@this.nospam.com), January 21, 2014 3:32 pm
Room: Moderated Discussions
>Nicolas Capens (nicolas.capens.delete@this.gmail.com) on January 20, 2014 3:48 pm wrote:
>> Stubabe (Stubabe.delete@this.nospam.com) on January 17, 2014 12:58 pm wrote:
> I assume the vector pipelines are in-order with a 4-cycle latency and round-robin scheduling, just like
> KNC. So the L0 cache does not affect scheduling. One L0 miss becomes an L1 access, so that's fine. Two
> L0 misses would create a bubble in one of the pipes, but that should be rare enough and cheap enough
You should assume no such thing - we don't know much about that yet. Also the Load unit IS scheduled out of order on Silvermont. So Load-op Instructions will issue to the load queues and then on completion to the FPU issue queue (in order or not) so the results have to be passed via the bypass network to the FPU (given the size of the operands it is very unlikely source operands are bundled with the instruction itself so will be read on issue - in fact Silvermont doesn't do this for power reasons). Note the FPU part of the instruction may have other dependencies so may have sit in the queue for a while. So either -> bypass network is large, complex with extensive FIFO etc -> i.e. power inefficient. Or more simply you allocate a temporary PRF entry and get the load unit to writeback to that (which obviously does not save a PRF access). Whatever you choose the mechanism has to handle the worst case for program correctness. Neither looks cheaper than a PRF access.
> That's exactly the load patterns we're observing in the examples Eric has posted. Remember,
> the L0 hit ratio does not have to be very high. It just allows to reuse memory operands without
> requiring a second L1 load port and to allow reducing the register file complexity.
>
Yes but the OoO is still throwing around lots of extra instructions to the load units filtered or not. That's more work right there. That's load queue slots and load issue bandwidth eaten up. All of that contributes to the cost benefit analysis you can't look at a hypothetical structure in solation and ignore the knock on effects elsewhere.
> First of all there are also continued savings from simplifying the register file. Secondly the
> L0 cache is utterly tiny so any cost is easily won back tenfold by hits. Look at the 'filter
> cache' and 'cached load/store queue' for similar very cheap additions with big savings.
An L0 with low hit rate will not allow you to make much difference to the register file especially if you want to support 3 operand instructions like FMA without stalls and other penalties. The absolute worst thing you can do for power on a OoO uarch is start introducing bubbles and micro-architectural hazards everywhere. Something that helps 10% of cases does nothing for the other 90% so better make sure the it doesn't introduce new issues of its own.
> > A far better explanation (if you really want to avoid two
> > load ports) is Load elimination (especially as Intel
> > actually have a patent filed for that) i.e. where identical
> > loads are eliminated by PRF redirection during rename.
> > But the only reason a complier would explicitly take advantage
> > of such a technique is to reduce total instruction
> > counts or to deal with register pressure, it would not offer power savings v normal register use.
>
> Why would it not save power? You're saving accessing the L1 cache for the same operand.
>
Obviously if loads are repeated as a natural function of code behaviour load elimination will be beneficial for both power and throughput. But a compiler actively using that mechanism over allocating a register when either method will just use a PRF read anyway will not save power. If anything it will use more as the load will have to matched to the preceding one and then effectively replaced by the operation the compiler could have explicitly used in the 1st place.
> the Haswell code looks as expected and it would be trivial to use it for the AVX-512. Compiler developers
> look at assembly output all day long, so this isn't something that just slipped their attention.
Its also silly unrepresentative microbenchmark code. Almost certainly not what the compiler is designed for: crap in -> crap out. I can produce lots of innocuous code sequences that randomly make otherwise good compilers suddenly vomit up crap only then to make a very sophisticated optimisation a few lines below. So yes I could easily believe it is a compiler issue as I have seen much worse (e.g. 32bit versions of the MSVC compiler often produce comically bad code but its not a problem restricted to MS).
>> Stubabe (Stubabe.delete@this.nospam.com) on January 17, 2014 12:58 pm wrote:
> I assume the vector pipelines are in-order with a 4-cycle latency and round-robin scheduling, just like
> KNC. So the L0 cache does not affect scheduling. One L0 miss becomes an L1 access, so that's fine. Two
> L0 misses would create a bubble in one of the pipes, but that should be rare enough and cheap enough
You should assume no such thing - we don't know much about that yet. Also the Load unit IS scheduled out of order on Silvermont. So Load-op Instructions will issue to the load queues and then on completion to the FPU issue queue (in order or not) so the results have to be passed via the bypass network to the FPU (given the size of the operands it is very unlikely source operands are bundled with the instruction itself so will be read on issue - in fact Silvermont doesn't do this for power reasons). Note the FPU part of the instruction may have other dependencies so may have sit in the queue for a while. So either -> bypass network is large, complex with extensive FIFO etc -> i.e. power inefficient. Or more simply you allocate a temporary PRF entry and get the load unit to writeback to that (which obviously does not save a PRF access). Whatever you choose the mechanism has to handle the worst case for program correctness. Neither looks cheaper than a PRF access.
> That's exactly the load patterns we're observing in the examples Eric has posted. Remember,
> the L0 hit ratio does not have to be very high. It just allows to reuse memory operands without
> requiring a second L1 load port and to allow reducing the register file complexity.
>
Yes but the OoO is still throwing around lots of extra instructions to the load units filtered or not. That's more work right there. That's load queue slots and load issue bandwidth eaten up. All of that contributes to the cost benefit analysis you can't look at a hypothetical structure in solation and ignore the knock on effects elsewhere.
> First of all there are also continued savings from simplifying the register file. Secondly the
> L0 cache is utterly tiny so any cost is easily won back tenfold by hits. Look at the 'filter
> cache' and 'cached load/store queue' for similar very cheap additions with big savings.
An L0 with low hit rate will not allow you to make much difference to the register file especially if you want to support 3 operand instructions like FMA without stalls and other penalties. The absolute worst thing you can do for power on a OoO uarch is start introducing bubbles and micro-architectural hazards everywhere. Something that helps 10% of cases does nothing for the other 90% so better make sure the it doesn't introduce new issues of its own.
> > A far better explanation (if you really want to avoid two
> > load ports) is Load elimination (especially as Intel
> > actually have a patent filed for that) i.e. where identical
> > loads are eliminated by PRF redirection during rename.
> > But the only reason a complier would explicitly take advantage
> > of such a technique is to reduce total instruction
> > counts or to deal with register pressure, it would not offer power savings v normal register use.
>
> Why would it not save power? You're saving accessing the L1 cache for the same operand.
>
Obviously if loads are repeated as a natural function of code behaviour load elimination will be beneficial for both power and throughput. But a compiler actively using that mechanism over allocating a register when either method will just use a PRF read anyway will not save power. If anything it will use more as the load will have to matched to the preceding one and then effectively replaced by the operation the compiler could have explicitly used in the 1st place.
> the Haswell code looks as expected and it would be trivial to use it for the AVX-512. Compiler developers
> look at assembly output all day long, so this isn't something that just slipped their attention.
Its also silly unrepresentative microbenchmark code. Almost certainly not what the compiler is designed for: crap in -> crap out. I can produce lots of innocuous code sequences that randomly make otherwise good compilers suddenly vomit up crap only then to make a very sophisticated optimisation a few lines below. So yes I could easily believe it is a compiler issue as I have seen much worse (e.g. 32bit versions of the MSVC compiler often produce comically bad code but its not a problem restricted to MS).
Topic | Posted By | Date |
---|---|---|
Knights Landing details (new article) | David Kanter | 2014/01/02 11:58 PM |
eDRAM as cache | iz | 2014/01/03 03:39 AM |
eDRAM options | Eric Bron | 2014/01/09 02:45 AM |
Knights Landing details (new article) | Emil Briggs | 2014/01/03 05:06 AM |
Knights Landing details (new article) | Michael S | 2014/01/03 06:05 AM |
PCI-E and QPI | David Kanter | 2014/01/03 11:11 AM |
eDRAM still seems too expensive ... | Mark Roulo | 2014/01/03 09:48 AM |
Nevermind ... I see that you addressed this :-) | Mark Roulo | 2014/01/03 09:51 AM |
eDRAM still seems too expensive ... | Eric Bron | 2014/01/03 12:42 PM |
eDRAM or stacked DRAM? | Patrick Chase | 2014/01/03 10:21 AM |
eDRAM or stacked DRAM? | Wes Felter | 2014/01/03 02:00 PM |
eDRAM or stacked DRAM? | Patrick Chase | 2014/01/03 06:26 PM |
eDRAM or stacked DRAM? | tarlinian | 2014/06/23 08:59 PM |
eDRAM or stacked DRAM? | Maynard Handley | 2014/06/24 12:47 AM |
eDRAM or stacked DRAM? | Michael S | 2014/06/24 02:13 AM |
eDRAM or stacked DRAM? | David Kanter | 2014/06/24 11:09 AM |
eDRAM or stacked DRAM? | anon | 2014/06/24 06:50 PM |
eDRAM or stacked DRAM? | Eric Bron | 2014/06/24 09:02 PM |
eDRAM or stacked DRAM? | anon | 2014/06/24 09:39 PM |
eDRAM or stacked DRAM? | Michael S | 2014/06/25 12:46 AM |
eDRAM or stacked DRAM? | Michael S | 2014/06/25 12:29 AM |
eDRAM or stacked DRAM? | Eric Bron | 2014/06/24 04:37 AM |
eDRAM or stacked DRAM? | tarlinian | 2014/06/24 07:53 AM |
eDRAM or stacked DRAM? | Eric Bron | 2014/06/24 08:09 AM |
eDRAM or stacked DRAM? | tarlinian | 2014/06/24 08:40 AM |
eDRAM or stacked DRAM? | Eric Bron | 2014/06/24 09:10 AM |
eDRAM or stacked DRAM? | Eric Bron | 2014/06/24 09:12 AM |
eDRAM or stacked DRAM? | Wes Felter | 2014/06/24 09:09 PM |
eDRAM or stacked DRAM? | Michael S | 2014/06/25 01:02 AM |
Why not tag-inclusive L3? | Paul A. Clayton | 2014/01/03 03:28 PM |
Why not tag-inclusive L3? | Eric Bron | 2014/01/04 02:22 AM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/04 04:43 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/04 05:20 AM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/04 01:55 PM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/04 02:27 PM |
Knights Landing L/S bandwidth | hobold | 2014/01/04 03:23 PM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/04 04:20 PM |
Knights Landing L/S bandwidth | Michael S | 2014/01/05 02:42 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/05 02:49 AM |
Knights Landing L/S bandwidth | Patrick Chase | 2014/01/11 07:13 PM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/13 07:39 PM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/05 02:18 PM |
Knights Landing L/S bandwidth | Michael S | 2014/01/06 03:09 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/06 04:11 AM |
Knights Landing L/S bandwidth | Michael S | 2014/01/06 04:40 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/06 04:54 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/08 08:00 AM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/07 02:31 PM |
Knights Landing L/S bandwidth | Michael S | 2014/01/07 03:17 PM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/07 08:55 PM |
Knights Landing L/S bandwidth | Michael S | 2014/01/08 12:42 AM |
Knights Landing L/S bandwidth | Gabriele Svelto | 2014/01/08 07:30 AM |
Occam's razor | Nicolas Capens | 2014/01/08 01:33 PM |
Occam's razor | Gabriele Svelto | 2014/01/08 01:51 PM |
Occam's razor | Eric Bron | 2014/01/08 02:28 PM |
Occam's razor | bakaneko | 2014/01/09 03:45 AM |
Occam's razor | anon | 2014/01/09 04:02 AM |
Occam's razor | bakaneko | 2014/01/09 05:24 AM |
Occam's razor | bakaneko | 2014/01/09 05:51 AM |
Occam's razor | anon | 2014/01/09 06:18 AM |
Occam's razor | anon | 2014/01/09 06:16 AM |
Occam's razor | bakaneko | 2014/01/09 07:43 AM |
Occam's razor | anon | 2014/01/09 08:17 AM |
Occam's razor | bakaneko | 2014/01/09 10:12 AM |
Occam's razor | Eric Bron | 2014/01/09 10:18 AM |
Occam's razor | bakaneko | 2014/01/09 10:58 AM |
Occam's razor | anon | 2014/01/09 11:35 AM |
Occam's razor | bakaneko | 2014/01/12 09:48 AM |
99.9% not a new extension | Nicolas Capens | 2014/01/10 10:39 AM |
Compiler complexity | Gabriele Svelto | 2014/01/11 02:58 AM |
Compiler complexity | Nicolas Capens | 2014/01/11 12:20 PM |
Compiler complexity | Gabriele Svelto | 2014/01/11 02:17 PM |
Patent pending | Nicolas Capens | 2014/01/14 06:21 PM |
99.9% not a new extension | bakaneko | 2014/01/12 10:08 AM |
L0 data cache | Eric Bron | 2014/01/08 03:52 PM |
Occam's razor | David Kanter | 2014/01/08 03:53 PM |
Occam's razor | Nicolas Capens | 2014/01/09 02:07 AM |
Occam's razor | Ricardo B | 2014/01/09 04:21 AM |
Virtually indexed, untagged | Nicolas Capens | 2014/01/10 10:27 AM |
Virtually indexed, untagged | Gabriele Svelto | 2014/01/11 03:08 AM |
Virtually indexed, untagged | Nicolas Capens | 2014/01/11 08:45 PM |
Virtually indexed, untagged | David Kanter | 2014/01/12 01:13 AM |
Virtually indexed, untagged | anon | 2014/01/12 03:02 AM |
Virtually indexed, untagged | Nicolas Capens | 2014/01/16 08:55 AM |
Virtually indexed, untagged | Michael S | 2014/01/12 03:09 AM |
Virtually indexed, untagged | Nicolas Capens | 2014/01/16 09:47 AM |
Occam's razor | David Kanter | 2014/01/09 05:42 PM |
Occam's razor | Nicolas Capens | 2014/01/10 01:22 PM |
Occam's razor | David Kanter | 2014/01/10 03:06 PM |
MEM : ALU ratio | Nicolas Capens | 2014/01/10 11:24 PM |
MEM : ALU ratio | Gabriele Svelto | 2014/01/11 02:47 AM |
MEM : ALU ratio | Eric Bron | 2014/01/11 03:41 AM |
MEM : ALU ratio | Eric Bron | 2014/01/11 04:06 AM |
MEM : ALU ratio | David Kanter | 2014/01/11 07:28 PM |
MEM : ALU ratio | Eric Bron nli | 2014/01/12 01:54 AM |
MEM : ALU ratio | Gabriele Svelto | 2014/01/11 09:15 AM |
MEM : ALU ratio | Nicolas Capens | 2014/01/14 05:56 PM |
Etiquette in linking to papers | Paul A. Clayton | 2014/01/14 06:44 PM |
MEM : ALU ratio | anon | 2014/01/14 07:32 PM |
L0 power cost | Nicolas Capens | 2014/01/16 01:05 PM |
L0 power cost | anon | 2014/01/16 09:01 PM |
L0 power cost | Nicolas Capens | 2014/01/18 11:30 PM |
Links revealed | Paul A. Clayton | 2014/01/19 03:47 PM |
L0 power cost | anon | 2014/01/20 12:19 AM |
L0 power cost | Nicolas Capens | 2014/01/20 01:49 PM |
L0 power cost | anon | 2014/01/21 12:18 AM |
Q.E.D. | Nicolas Capens | 2014/01/21 07:44 PM |
Q.E.D. | anon | 2014/01/21 08:24 PM |
Straw man | Nicolas Capens | 2014/01/23 10:56 PM |
Straw man | anon | 2014/01/25 05:46 AM |
Still waiting for an explanation | Nicolas Capens | 2014/01/25 11:19 PM |
Still waiting for an explanation | Exophase | 2014/01/26 12:13 PM |
Still waiting for an explanation | bakaneko | 2014/01/26 10:52 PM |
Q.E.D. | Ricardo B | 2014/01/22 05:58 PM |
Q.E.D. | Michael S | 2014/01/23 03:59 AM |
L0 entry count | Nicolas Capens | 2014/01/24 12:11 AM |
L0 entry count | Eric Bron | 2014/01/24 01:08 AM |
L0 entry count | Michael S | 2014/01/24 05:18 AM |
L0 entry count | Eric Bron | 2014/01/24 06:15 AM |
L0 entry count | Michael S | 2014/01/24 07:10 AM |
L0 entry count | Eric Bron | 2014/01/24 07:20 AM |
L0 entry count | Nicolas Capens | 2014/01/24 01:33 PM |
L0 entry count | Eric Bron | 2014/01/24 02:20 PM |
L0 entry count and L1 read port orthogonality | Nicolas Capens | 2014/01/26 12:14 AM |
L0 entry count and L1 read port orthogonality | Eric Bron | 2014/01/26 02:49 AM |
L0 hit rate | Nicolas Capens | 2014/01/23 11:49 PM |
L0 hit rate | Ricardo B | 2014/01/24 05:42 AM |
L0 hit rate | Exophase | 2014/01/24 12:37 PM |
L0 hit rate | Eric Bron | 2014/01/24 01:12 PM |
L0 vs RF power | Nicolas Capens | 2014/01/24 01:43 PM |
MEM : ALU ratio | David Kanter | 2014/01/11 12:47 PM |
MEM : ALU ratio | Nicolas Capens | 2014/01/16 08:23 AM |
MEM : ALU ratio | Stubabe | 2014/01/17 11:58 AM |
MEM : ALU ratio | Stubabe | 2014/01/17 12:42 PM |
MEM : ALU ratio | Michael S | 2014/01/18 03:57 PM |
MEM : ALU ratio | bakaneko | 2014/01/18 11:47 PM |
MEM : ALU ratio | Nicolas Capens | 2014/01/20 02:48 PM |
It's called "tunnel vision" (NT) | iz | 2014/01/20 03:36 PM |
MEM : ALU ratio | Michael S | 2014/01/20 03:37 PM |
MEM : ALU ratio | Stubabe | 2014/01/21 03:54 PM |
MEM : ALU ratio | Nicolas Capens | 2014/01/21 09:07 PM |
MEM : ALU ratio | Michael S | 2014/01/22 07:17 AM |
MEM : ALU ratio | Nicolas Capens | 2014/01/24 02:33 PM |
MEM : ALU ratio | Stubabe | 2014/01/21 03:32 PM |
MEM : ALU ratio | Michael S | 2014/01/22 07:56 AM |
MEM : ALU ratio | Stubabe | 2014/01/23 08:06 AM |
MEM : ALU ratio | Eric Bron | 2014/01/23 08:45 AM |
edit | Eric Bron | 2014/01/23 08:49 AM |
MEM : ALU ratio | Michael S | 2014/01/23 08:58 AM |
MEM : ALU ratio | Eric Bron | 2014/01/23 09:29 AM |
MEM : ALU ratio | Michael S | 2014/01/23 09:33 AM |
MEM : ALU ratio | Stubabe | 2014/01/24 03:50 AM |
MEM : ALU ratio | bakaneko | 2014/01/23 09:36 AM |
MEM : ALU ratio | NoSpammer | 2014/01/11 02:39 PM |
L1 vs L0 access cost | Nicolas Capens | 2014/01/16 02:17 PM |
L1 vs L0 access cost | NoSpammer | 2014/01/19 12:48 PM |
L1 vs L0 access cost | dmcq | 2014/01/22 04:45 AM |
L1 vs L0 access cost | Gabriele Svelto | 2014/01/22 06:29 AM |
L1 vs L0 access cost | dmcq | 2014/01/22 12:33 PM |
L1 vs L0 access cost | Gabriele Svelto | 2014/01/22 03:33 PM |
L1 vs L0 access cost | dmcq | 2014/01/24 03:19 AM |
L1 vs L0 access cost | Nicolas Capens | 2014/01/24 01:16 AM |
Occam's razor | Patrick Chase | 2014/01/13 10:19 AM |
Occam's razor | Nicolas Capens | 2014/01/08 11:40 PM |
Occam's razor | Gabriele Svelto | 2014/01/09 01:41 AM |
Occam's razor | Eric Bron | 2014/01/09 01:54 AM |
Occam's razor | Gabriele Svelto | 2014/01/09 05:35 AM |
Occam's razor | Eric Bron | 2014/01/09 06:14 AM |
avoiding redundant loads | Eric Bron | 2014/01/09 06:18 AM |
AVX2 version | Eric Bron | 2014/01/09 06:32 AM |
Occam's razor | Amiba Gelos | 2014/01/09 02:01 AM |
Occam's razor | Eric Bron | 2014/01/09 02:06 AM |
Occam's razor | Amiba Gelos | 2014/01/09 02:43 AM |
Occam's razor | Eric Bron | 2014/01/09 03:02 AM |
L0 access latency | Nicolas Capens | 2014/01/09 03:27 AM |
L0 access latency | Amiba Gelos | 2014/01/09 04:16 AM |
compared to L0$ i would say banking is far more likely (NT) | Amiba Gelos | 2014/01/09 04:20 AM |
L0 access latency | Nicolas Capens | 2014/01/10 02:20 PM |
Occam's razor | Nicolas Capens | 2014/01/09 03:19 AM |
Occam's razor | NoSpammer | 2014/01/09 11:55 AM |
Occam's razor | Nicolas Capens | 2014/01/10 02:40 PM |
Occam's razor | Michael S | 2014/01/11 09:21 AM |
Occam's razor | Michael S | 2014/01/12 02:21 PM |
KNC compiler output | Nicolas Capens | 2014/01/16 05:39 PM |
KNC compiler output | Michael S | 2014/01/18 04:13 PM |
L0 cache coherency | David Kanter | 2014/01/11 07:39 PM |
Occam's razor | anon | 2014/01/09 04:12 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/08 09:46 AM |
Knights Landing L/S bandwidth | Michael S | 2014/01/08 10:23 AM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/08 01:02 PM |
Knights Landing L/S bandwidth | Michael S | 2014/01/08 01:29 PM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/08 01:54 PM |
Knights Landing L/S bandwidth | Michael S | 2014/01/08 02:00 PM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/08 02:13 PM |
Knights Landing L/S bandwidth | Michael S | 2014/01/08 02:28 PM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/08 02:32 PM |
Knights Landing L/S bandwidth | Michael S | 2014/01/08 02:40 PM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/08 02:51 PM |
Knights Landing L/S bandwidth | Michael S | 2014/01/09 11:18 AM |
Knights Landing L/S bandwidth | Patrick Chase | 2014/01/12 09:03 PM |
Also page/line splits? | David Kanter | 2014/01/12 09:50 PM |
Also page/line splits? | anon | 2014/01/13 12:44 AM |
Also page/line splits? | none | 2014/01/13 02:09 AM |
Also page/line splits? | anon | 2014/01/13 03:19 AM |
Knights Landing L/S bandwidth | Exophase | 2014/01/12 11:15 PM |
Knights Landing L/S bandwidth | anon | 2014/01/13 12:41 AM |
Knights Landing L/S bandwidth | Patrick Chase | 2014/01/13 10:14 AM |
Aliased writes | Nicolas Capens | 2014/01/14 08:46 PM |
Knights Landing L/S bandwidth | Ricardo B | 2014/01/07 03:27 PM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/07 09:28 PM |
Knights Landing L/S bandwidth | Ricardo B | 2014/01/08 01:13 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/08 10:10 AM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/08 02:31 PM |
Knights Landing L/S bandwidth | Ricardo B | 2014/01/08 02:58 PM |
Knights Landing L/S bandwidth | G. Gouvine | 2014/01/09 08:10 AM |
Knights Landing L/S bandwidth | Ricardo B | 2014/01/09 10:19 AM |
Efficient load queue vs. efficient L0 cache | Nicolas Capens | 2014/01/11 11:28 AM |
Efficient load queue vs. efficient L0 cache | G. Gouvine | 2014/01/13 01:11 AM |
Efficient load queue vs. efficient L0 cache | Michael S | 2014/01/13 02:43 AM |
Register file read port requirements | Nicolas Capens | 2014/01/10 11:55 PM |
Register file read port requirements | Ricardo B | 2014/01/11 04:24 AM |
Register file read port requirements | Eric Bron | 2014/01/11 04:32 AM |
Register file read port requirements | Michael S | 2014/01/11 08:57 AM |
Register file read port requirements | Eric Bron | 2014/01/11 10:16 AM |
Register file read port requirements | Michael S | 2014/01/11 10:46 AM |
Register file read port requirements | Eric Bron | 2014/01/11 11:12 AM |
Register file read port requirements | Michael S | 2014/01/11 11:36 AM |
Register file read port requirements | Eric Bron | 2014/01/11 11:51 AM |
Register file read port requirements | Patrick Chase | 2014/01/13 01:27 PM |
Register file read port requirements | Eric Bron | 2014/01/13 03:24 PM |
Register file read port requirements | Patrick Chase | 2014/01/13 05:02 PM |
Register file read port requirements | Eric Bron | 2014/01/14 03:50 AM |
Register file read port requirements | Michael S | 2014/01/14 10:36 AM |
Register file read port requirements | Eric Bron nli | 2014/01/14 12:04 PM |
Register file read port requirements | Patrick Chase | 2014/01/13 01:17 PM |
Register file read port requirements | Michael S | 2014/01/15 03:27 AM |
Register file read port requirements | Eric Bron | 2014/01/11 10:28 AM |
Register file read port requirements | Michael S | 2014/01/11 11:07 AM |
Register file read port requirements | Patrick Chase | 2014/01/13 01:40 PM |
Register file read port requirements | Patrick Chase | 2014/01/13 01:34 PM |
Register file read port requirements | Ricardo B | 2014/01/11 11:55 AM |
Register file read port requirements | Eric Bron | 2014/01/11 12:17 PM |
Register file read port requirements | Ricardo B | 2014/01/11 01:36 PM |
Register file read port requirements | Eric Bron | 2014/01/11 01:42 PM |
Register file read port requirements | Ricardo B | 2014/01/11 02:20 PM |
Register file read port requirements | Eric Bron | 2014/01/11 02:26 PM |
Register file read port requirements | Michael S | 2014/01/11 03:07 PM |
Register file read port requirements | Ricardo B | 2014/01/11 03:38 PM |
Register file read port requirements | Michael S | 2014/01/11 03:49 PM |
Register file read port requirements | Eric Bron | 2014/01/11 02:39 PM |
Register file read port requirements | Eric Bron | 2014/01/11 02:41 PM |
Register file read port requirements | Ricardo B | 2014/01/11 03:30 PM |
Register file read port requirements | Nicolas Capens | 2014/01/11 11:09 AM |
Knights Landing L/S bandwidth | anon | 2014/01/05 05:55 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/05 06:30 AM |
Knights Landing L/S bandwidth | anon | 2014/01/06 12:07 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/06 01:38 AM |
Knights Landing L/S bandwidth | anon | 2014/01/06 03:01 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/06 03:44 AM |
Knights Landing L/S bandwidth | anon | 2014/01/06 04:39 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/06 05:00 AM |
Knights Landing L/S bandwidth | anon | 2014/01/06 05:44 AM |
Knights Landing L/S bandwidth | Michael S | 2014/01/06 07:54 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/06 09:11 AM |
Knights Landing L/S bandwidth | Michael S | 2014/01/06 09:14 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/06 10:37 AM |
Knights Landing L/S bandwidth | Ricardo B | 2014/01/08 05:25 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/08 07:36 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/08 07:41 AM |
KNC code generator with EVEX back-end? | Michael S | 2014/01/08 08:43 AM |
KNC code generator with EVEX back-end? | Exophase | 2014/01/08 09:00 AM |
KNC code generator with EVEX back-end? | Ricardo B | 2014/01/08 10:39 AM |
KNC code generator with EVEX back-end? | Eric Bron | 2014/01/08 11:15 AM |
KNC code generator with EVEX back-end? | Exophase | 2014/01/08 12:17 PM |
KNC code generator with EVEX back-end? | Ricardo B | 2014/01/08 01:06 PM |
KNC code generator with EVEX back-end? | Exophase | 2014/01/08 01:24 PM |
KNC code generator with EVEX back-end? | Eric Bron | 2014/01/08 01:38 PM |
KNC code generator with EVEX back-end? | Michael S | 2014/01/08 12:54 PM |
KNC code generator with EVEX back-end? | Eric Bron | 2014/01/08 09:25 AM |
KNC code generator with EVEX back-end? | Eric Bron | 2014/01/08 09:35 AM |
KNC code generator with EVEX back-end? | Michael S | 2014/01/08 10:07 AM |
KNC code generator with EVEX back-end? | Eric Bron | 2014/01/08 10:24 AM |
KNC code generator with EVEX back-end? | Michael S | 2014/01/08 10:43 AM |
KNC code generator with EVEX back-end? | Eric Bron | 2014/01/08 12:23 PM |
KNC code generator with EVEX back-end? | Eric Bron | 2014/01/08 09:43 AM |
AVX2 code much different than AVX-512 | Eric Bron | 2014/01/08 07:52 AM |
evil question | hobold | 2014/01/08 09:22 AM |
evil question | Eric Bron | 2014/01/08 09:27 AM |
evil question | hobold | 2014/01/08 01:33 PM |
evil question | Michael S | 2014/01/08 01:37 PM |
stupid question (was: evil question) | hobold | 2014/01/09 04:41 AM |
stupid question (was: evil question) | Eric Bron | 2014/01/09 04:52 AM |
stupid question (was: evil question) | Michael S | 2014/01/09 07:00 AM |
stupid question (was: evil question) | Michael S | 2014/01/09 07:12 AM |
stupid question (was: evil question) | Eric Bron | 2014/01/09 09:47 AM |
stupid question (was: evil question) | Michael S | 2014/01/09 10:48 AM |
more decisive (hopefully) test case | Michael S | 2014/01/09 11:01 AM |
more decisive (hopefully) test case | Eric Bron | 2014/01/09 11:08 AM |
more decisive (hopefully) test case | Michael S | 2014/01/09 11:24 AM |
more decisive (hopefully) test case | Eric Bron | 2014/01/09 11:27 AM |
more decisive (hopefully) test case | Michael S | 2014/01/09 11:33 AM |
AVX2 | Eric Bron | 2014/01/09 11:14 AM |
AVX2 | Michael S | 2014/01/09 11:30 AM |
AVX2 | Eric Bron | 2014/01/09 11:40 AM |
another try | Michael S | 2014/01/09 02:02 PM |
another try | Eric Bron | 2014/01/09 02:33 PM |
another try | Michael S | 2014/01/09 03:20 PM |
another try - ignore misformated mess above | Michael S | 2014/01/09 03:24 PM |
another try - ignore misformated mess above | Gabriele Svelto | 2014/01/10 12:01 AM |
another try - ignore misformated mess above | Eric Bron | 2014/01/10 02:05 AM |
another try - ignore misformated mess above | Michael S | 2014/01/11 09:23 AM |
another try - ignore misformated mess above | Eric Bron | 2014/01/11 10:08 AM |
another try - ignore misformated mess above | Michael S | 2014/01/11 11:09 AM |
another try - ignore misformated mess above | Michael S | 2014/01/11 11:12 AM |
another try - ignore misformated mess above | Eric Bron | 2014/01/11 11:24 AM |
another try - ignore misformated mess above | Michael S | 2014/01/11 12:24 PM |
another try - ignore misformated mess above | Eric Bron | 2014/01/11 01:11 PM |
another try - ignore misformated mess above | Michael S | 2014/01/11 01:18 PM |
another try - ignore misformated mess above | Eric Bron | 2014/01/11 01:27 PM |
another try - ignore misformated mess above | Michael S | 2014/01/11 01:29 PM |
another try - ignore misformated mess above | Eric Bron | 2014/01/11 01:46 PM |
another try - ignore misformated mess above | Eric Bron | 2014/01/11 01:46 PM |
another try - ignore misformated mess above | Michael S | 2014/01/11 02:28 PM |
another try - ignore misformated mess above | Eric Bron | 2014/01/11 01:17 PM |
another try - ignore misformated mess above | Michael S | 2014/01/11 01:24 PM |
KNC version | Michael S | 2014/01/11 04:19 PM |
KNC version | Eric Bron nli | 2014/01/12 01:59 AM |
KNC version | Gabriele Svelto | 2014/01/12 08:06 AM |
evil question | Eric Bron | 2014/01/08 01:41 PM |
Knights Landing L/S bandwidth | Patrick Chase | 2014/01/05 10:20 PM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/06 01:45 AM |
Knights Landing L/S bandwidth | anon | 2014/01/06 03:12 AM |
Knights Landing L/S bandwidth | Michael S | 2014/01/06 03:17 AM |
Knights Landing L/S bandwidth | anon | 2014/01/06 04:20 AM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/04 04:34 PM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/04 04:44 PM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/05 11:25 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/05 12:50 PM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/05 02:34 PM |
Might even help with gather | Nicolas Capens | 2014/01/05 02:40 PM |
What is an L0 cache? | David Kanter | 2014/01/05 09:44 PM |
What is an L0 cache? | anon | 2014/01/06 04:57 AM |
What is an L0 cache? | Nicolas Capens | 2014/01/06 11:57 AM |
What is an L0 cache? | anon | 2014/01/06 01:18 PM |
Knights Landing L/S bandwidth | David Kanter | 2014/01/04 09:58 AM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/04 03:24 PM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/04 03:46 PM |
Knights Landing L/S bandwidth | Konrad Schwarz | 2014/01/07 11:48 PM |
Knights Landing L/S bandwidth | Michael S | 2014/01/08 01:45 AM |
Knights Landing L/S bandwidth | David Kanter | 2014/01/05 12:44 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/05 02:55 AM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/05 11:18 AM |
Knights Landing L/S bandwidth | Maynard Handley | 2014/01/05 10:33 PM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/06 03:02 AM |
Knights Landing L/S bandwidth | Michael S | 2014/01/06 03:23 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/06 03:35 AM |
Knights Landing L/S bandwidth | Michael S | 2014/01/06 04:20 AM |
Knights Landing L/S bandwidth | Michael S | 2014/01/06 04:32 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/06 04:36 AM |
Knights Landing L/S bandwidth | Michael S | 2014/01/06 05:00 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/06 05:07 AM |
Knights Landing L/S bandwidth | Eric Bron | 2014/01/06 05:14 AM |
edits | Eric Bron | 2014/01/06 05:22 AM |
optimized version | Eric Bron | 2014/01/06 05:35 AM |
yet more optimized version | Eric Bron | 2014/01/06 05:42 AM |
latest version for today | Eric Bron | 2014/01/06 05:51 AM |
Probably just L2 bandwith limited | Nicolas Capens | 2014/01/06 10:48 AM |
yet more optimized version | Maynard Handley | 2014/01/06 05:54 PM |
optimized version | Maynard Handley | 2014/01/06 05:52 PM |
optimized version | Michael S | 2014/01/07 09:42 AM |
optimized version | Nicolas Capens | 2014/01/07 11:36 AM |
optimized version | Michael S | 2014/01/07 02:41 PM |
optimized version | Nicolas Capens | 2014/01/07 09:52 PM |
optimized version | Michael S | 2014/01/08 01:10 AM |
optimized version | Eric Bron | 2014/01/07 01:34 PM |
optimized version | Michael S | 2014/01/07 02:18 PM |
optimized version | Eric Bron | 2014/01/07 02:30 PM |
optimized version | Eric Bron | 2014/01/07 02:33 PM |
optimized version | Michael S | 2014/01/07 02:57 PM |
optimized version | Maynard Handley | 2014/01/07 05:50 PM |
optimized version | Michael S | 2014/01/08 01:39 AM |
Knights Landing L/S bandwidth | Maynard Handley | 2014/01/06 05:47 PM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/06 08:18 AM |
Knights Landing L/S bandwidth | Maynard Handley | 2014/01/06 05:56 PM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/07 11:18 AM |
Knights Landing L/S bandwidth | NoSpammer | 2014/01/05 12:15 PM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/05 02:06 PM |
Knights Landing L/S bandwidth | NoSpammer | 2014/01/06 03:20 AM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/06 10:54 AM |
Knights Landing L/S bandwidth | NoSpammer | 2014/01/06 12:24 PM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/06 08:15 PM |
Knights Landing L/S bandwidth | NoSpammer | 2014/01/07 02:58 AM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/07 02:18 PM |
Knights Landing L/S bandwidth | NoSpammer | 2014/01/08 12:38 PM |
Knights Landing L/S bandwidth | Nicolas Capens | 2014/01/08 10:14 PM |
AVX512F question | Michael S | 2014/01/06 09:18 AM |
AVX512F question | Nicolas Capens | 2014/01/06 11:01 AM |
Knights Landing - time for obituary? | Michael S | 2018/07/31 02:00 PM |
Knights Landing - time for obituary? | Adrian | 2018/07/31 08:24 PM |
Knights Landing - time for obituary? | SoftwareEngineer | 2018/08/01 01:15 AM |
auto-vectorization is a dead end | Michael S | 2018/08/01 02:48 AM |
Auto-vectorization of random C is a dead end | Mark Roulo | 2018/08/01 10:07 AM |
Auto-vectorization of random C is a dead end | Passing Through | 2018/08/01 12:35 PM |
Auto-vectorization of random C is a dead end | David Kanter | 2018/08/01 09:44 PM |
Auto-vectorization of random C is a dead end | Passing Through | 2018/08/02 12:51 AM |
Auto-vectorization of random C is a dead end | SoftwareEngineer | 2018/08/02 12:19 AM |
Auto-vectorization of random C is a dead end | Mark Roulo | 2018/08/02 08:50 AM |
Auto-vectorization of random C is a dead end | Michael S | 2018/08/02 11:11 AM |
Auto-vectorization of random C is a dead end | j | 2018/08/02 10:37 PM |
Auto-vectorization of random C is a dead end | Michael S | 2018/08/03 02:50 AM |
Auto-vectorization of random C is a dead end | rwessel | 2018/08/03 10:06 PM |
Auto-vectorization of random C is a dead end | Ricardo B | 2018/08/03 03:20 AM |
Auto-vectorization of random C is a dead end | Michael S | 2018/08/03 04:37 AM |
Auto-vectorization of random C is a dead end | Ricardo B | 2018/08/03 10:22 AM |
Auto-vectorization of random C is a dead end | Travis | 2018/08/03 06:58 PM |
Potential way to autovectorization in the future. | Jouni Osmala | 2018/08/03 09:22 PM |
Potential way to autovectorization in the future. | Jukka Larja | 2018/08/04 03:03 AM |
Potential way to autovectorization in the future. | Passing Through | 2018/08/04 05:47 AM |
Potential way to autovectorization in the future. | Travis | 2018/08/04 12:50 PM |
Potential way to autovectorization in the future. | Michael S | 2018/08/04 01:33 PM |
Potential way to autovectorization in the future. | Travis | 2018/08/04 01:48 PM |
Potential way to autovectorization in the future. | Passing Through | 2018/08/04 01:58 PM |
Skylake server/client AVX PRF speculation | Jeff S. | 2018/08/04 04:42 PM |
Skylake server/client AVX PRF speculation | anonymou5 | 2018/08/04 05:21 PM |
Skylake server/client AVX PRF speculation | Jeff S. | 2018/08/04 05:38 PM |
Skylake server/client AVX PRF speculation | anonymou5 | 2018/08/04 06:45 PM |
Skylake server/client AVX PRF speculation | Jeff S. | 2018/08/04 07:08 PM |
Skylake server/client AVX PRF speculation | anonymou5 | 2018/08/04 07:18 PM |
Skylake server/client AVX PRF speculation | Nomad | 2018/08/05 10:10 PM |
Skylake server/client AVX PRF speculation | anonymou5 | 2018/08/06 11:14 AM |
Skylake server/client AVX PRF speculation | Travis | 2018/08/06 07:43 PM |
Skylake server/client AVX PRF speculation | Travis | 2018/08/06 07:39 PM |
Auto-vectorization of random C is a dead end | Brett | 2018/08/04 12:55 PM |
Auto-vectorization of random C is a dead end | Travis | 2018/08/04 01:38 PM |
Auto-vectorization of random C is a dead end | Passing Through | 2018/08/04 02:00 PM |
New record for shortest post by Ireland - AI crashed? (NT) | Travis | 2018/08/04 02:34 PM |
New record for shortest post by Ireland - AI crashed? | Passing Through | 2018/08/04 03:12 PM |
New record for shortest post by Ireland - AI crashed? | anonymou5 | 2018/08/04 05:00 PM |
New record for shortest post by Ireland - AI crashed? | Brett | 2018/08/04 05:40 PM |
New record for shortest post by Ireland - AI crashed? | anonymou5 | 2018/08/04 06:38 PM |
Auto-vectorization of random C is a dead end | noko | 2018/08/04 08:46 PM |
The story of ispc (a 12 entry blog series) | Simon Farnsworth | 2018/08/01 02:50 AM |
the 1st link is empty (NT) | Michael S | 2018/08/01 03:05 AM |
the 1st link is empty | Simon Farnsworth | 2018/08/01 05:42 AM |
Interesting read, thanks! (NT) | SoftwareEngineer | 2018/08/01 05:57 AM |
Amazing read | Laurent | 2018/08/01 08:00 AM |
Amazing read | Passing Through | 2018/08/01 12:13 PM |
Amazing read | Doug S | 2018/08/01 01:30 PM |
Amazing read | Passing Through | 2018/08/01 01:49 PM |
ISPC vs OpenCL? | j | 2018/08/02 10:41 PM |
ISPC vs OpenCL? | coppcie | 2018/08/03 02:55 AM |
ISPC vs OpenCL? | Passing Through | 2018/08/03 03:07 AM |
Go away | Forum Reader | 2018/08/03 07:11 AM |
ISPC vs OpenCL? | Gian-Carlo Pascutto | 2018/09/11 05:50 AM |
ISPC vs OpenCL? | SoftwareEngineer | 2018/08/03 03:18 AM |
Knights Landing - time for obituary? | Kevin G | 2018/08/01 06:14 AM |
Knights Landing - time for obituary? | SoftwareEngineer | 2018/08/01 06:29 AM |
Knights Landing - time for obituary? | Passing Through | 2018/08/01 06:38 AM |
Knights Landing - time for obituary? | Eric Bron | 2018/08/02 05:57 AM |
Knights Landing - time for obituary? | Passing Through | 2018/08/02 11:29 AM |
Knights Landing - time for obituary? | Eric Bron | 2018/08/02 12:49 PM |
Knights Landing - time for obituary? | Passing Through | 2018/08/02 01:17 PM |
chess algorithms vs, low level optimizations | Eric Bron | 2018/08/02 06:15 AM |
AlphaZero vs Stockfish | Michael S | 2018/08/02 06:55 AM |
AlphaZero vs Stockfish | Eric Bron | 2018/08/02 07:24 AM |
AlphaZero vs Stockfish | Michael S | 2018/08/02 08:01 AM |
AlphaZero vs Stockfish | Eric Bron | 2018/08/02 08:11 AM |
Leela 4th vs all others | Eric Bron nli | 2018/09/11 02:40 AM |
AlphaZero vs Stockfish | Gian-Carlo Pascutto | 2018/09/11 05:31 AM |
AlphaZero vs Stockfish | Eric Bron | 2018/09/11 08:26 AM |
AlphaZero vs Stockfish | Eric Bron | 2018/09/11 08:58 AM |
AlphaZero vs Stockfish | Per Hesselgren | 2018/12/31 09:04 AM |
Leela Chess Zero | Per Hesselgren | 2018/12/31 11:00 AM |
AlphaZero vs Stockfish (on Xeon) | Per Hesselgren | 2018/12/31 08:59 AM |
C/C++ and vector/parallel/distributed | RichardC | 2018/08/02 04:50 AM |
Knights Landing - time for obituary? | Passing Through | 2018/08/01 06:52 AM |
Knights Landing - time for obituary? | Kevin G | 2018/08/01 01:03 PM |
Knights Landing - time for obituary? | Passing Through | 2018/08/01 01:33 PM |
Knights Landing - time for obituary? | Kevin G | 2018/08/01 07:26 AM |
Knights Landing - time for obituary? | Kevin G | 2018/08/01 07:26 AM |
Knights Landing - time for obituary? | juanrga | 2018/08/01 01:26 PM |
Knights Landing - time for obituary? | hobel | 2018/08/02 04:46 AM |
Knights Landing - time for obituary? | juanrga | 2018/07/31 10:25 PM |
Right, time for obituary for whole LRB lineage | AM | 2018/08/02 10:46 AM |
Right, time for obituary for whole LRB lineage | Adrian | 2018/08/02 10:46 PM |
LRBNI, AVX512, etc... | Michael S | 2018/08/03 04:23 AM |
Right, time for obituary for whole LRB lineage | juanrga | 2018/08/03 03:11 AM |