Nicolas Capens (nicolas.capens.delete@this.gmail.com) on January 21, 2014 8:44 pm wrote:
>
> On the contrary. "The Filter Cache: An Energy Efficient Memory Structure" (Johnson Kin et al., 1997)
> examines caches of up to 256 bytes and still concludes them to save a considerable amount of power,
> while line buffers are typically just a single cache line. So if the filter cache is power efficient,
> why not the symbolic L0 cache which doesn't even require addresses to be computed?

I've already addressed in reply to other poster.

Hit rate, hit rate, hit rate.
Those papers are evaluating tiny caches for scalar workloads, where they actually get good enough hit rates to save power and time.

Considering the most favorable case, if you have a workload that consists on sequential access of an array of 8 bit elements, you'll serve 32 memory operations from a single 32B cache line.
If the ISA has load/store-double, you can reduce it to 16 memory operations per cache line.
In any case, this pattern alone will give you a good reuse of your cache line (as long as there isn't thrashing).
Other patterns, like accessing the multiple fields of a structure or spilling/filling registers onto the stack, can also provide good localized accesses on single cache lines.

On the other extreme, if you vectorize the workload with 256-bit SIMD, you will only need a single memory access per 32B cache line.
So, you get no re-use of your cache line from there.

The fundamental issue with your proposal is that is too small for the workload in question: a 4x64B cache only holds 4x512-bit elements.