Kevin G (kevin.delete@this.cubitdesigns.com) on August 1, 2018 8:26 am wrote:
> Adrian (a.delete@this.acm.org) on July 31, 2018 9:24 pm wrote:
> > Michael S (already5chosen.delete@this.yahoo.com) on July 31, 2018 3:00 pm wrote:
> > >
> > > Select Intel® Xeon Phi™ Processors:
> > > 7210, 7210F, 7230, 7230F, 7250, 7250F,7290, and 7290F,
> > > PCN 116378-00, Product Discontinuance,
> > > End of Life
> > > https://qdms.intel.com/dm/i.aspx/9C54A9A7-BF37-4496-B268-BD2746EA54D3/PCN116378-00.pdf
> > >
> > > Barely lasted 2 years.
> >
> >
> > If the processors would be able to reach the same percentage of the peak speed,
> > then Xeon Phi would have 1/2 of the performance per watt of NVIDIA Volta while
> > Xeon Platinum would have 1/3 of the performance per watt of NVIDIA Volta.
> >
> > (Off topic, while GPUs are without doubt the most efficient, the ratio 1/3, which was valid
> > for the last several generations of Intel & NVIDIA is very far from the ridiculous ratios,
> > such as 100, which were claimed in all the early propaganda papers about GPGPU.)
>
> Both Intel and nVidia hit the power wall and process shrinks have slowed to a crawl.
> nVidia has take the rather extreme measure of going with a 815 mm^2 die plus the
> addition of HBM on an interposer to continue their performance scaling.
>
> > Nevertheless, the very little information that I have seen about the real speed attainable by Xeon Phi,
> > suggest that in fact the percentage of the peak speed reached by Xeon Phi is around 2/3 of the percentage
> > reached by Xeon Platinum. Therefore the real performance per watt is about the same for both.
>
> KNL was also released two years before the Xeon Platinums.
>
> > Then the only advantage remaining for Xeon Phi is that, at the official prices, its performance
> > per dollar is much better than for NVIDIA Volta and for Xeon Platinum or Gold.
> >
> > This is offset by the reports that claim that optimizing programs
> > for Xeon Phi is much more difficult than for the alternatives.
>
> Optimization costs are going to be incurred regardless of platform. KNL claim to fame
> was easy porting of code in an unoptimized state. So if the HPC installation was running
> x86 based code before, getting it up and running in an unoptimized state on KNL was trivial.
> That part of the story did happen in a few places from what I've read.
>
> > Since Xeon Phi does not appear to have enough advantages over its competitors, there is no surprise
> > in the end-of-life announcements and in the Intel roadmaps which show that the successors of Xeon
> > Phi will be high-core-count MCM derivatives of the mainstream Xeon Scalable products.
>
> There is still one advantage: memory capacity. Being able to attach 384 GB of DDR4 in addition
> to the 16 GB of HMC permits some rather large and local data sets per node. Leaked road maps
> point toward a Knights Landing refresh which is supposed to add 3D Xpoint DIMM support for even
> higher memory capacity. It is unclear if this refresh will see the light of day though.
>
> Remote access of CPU from nVidia's recent GPUs is possible but incurs a performance hit due to latency.
>
> > Still, it is not clear for me why this has ended so. There seems nothing wrong about the concept
> > that a throughput-optimized processor should have a large number of dual-issue in-order cores with
> > large SIMD units. This seems the obvious way to get high performance per watt and per dollar.
> >
> > The main problem with Xeon Phi, its difficulties in reaching high percentages
> > of its peak speed, do not seem related with the general concept, but seem to
> > have been caused by various implementation quirks of Knights Landing.
>
> Xeon Platinums also have difficulties maintaining peak performance. L2cache bandwidth is the
> believed to be the bottleneck. The hardware is there for two AVX-512 operations per clock throughput
> but the L2 caches cannot keep up. The L1 cache has the bandwidth but at 32 KB there isn't much
> room. L3 cache has a relatively high latency to compound matters even more.
>
> > At least this is what I have seen in the few published analyses
> > of its microarchitecture, e.g. that from Agner Fog.
> >
> > Has anyone of you seen any papers which analyse the causes of inefficiency in Xeon Phi ?
> >
> > I believe that maybe the failure of Xeon Phi was caused by its design
> > by a B team and by the rush to market of an immature implementation.
>
> The successor to Knights Landing, Knights Hill was tied to the 10 nm process. Some IPC improvements
> were to be incorporated with the Goldmont+ core design seen in some Atoms. Bandwidth and capacity
> increases for on package memory was also promised. No memory type was specified but Intel was the
> main backer behind HMC and it doesn't appear that HMC2 is ready for mass production. It is conceptually
> possible that another reason for Knights Hill death came from the memory side of things.
>
> After Knights Hill it would have made sense for Intel to migrate to a chiplet based designs using
> EMIB to scale up core counts to insane levels. HPC is one of the few areas where such manufacturing
> costs could be reasonably absorbed. This would have also side stepped the current yield issues
> on 10 nm as it is far easier to harvest smaller chiplet sized dies than huge monoliths.
>
> nVidia last year released a paper on their own chiplet research.
>
> > I think that it is bad that the failure of Xeon Phi has tainted this idea. For me, the ideal computer
> > would be a 2-socket machine, where one socket would have a 2-core or 4-core 5 GHz OOOE processor, but
> > the other socket would have very-high-core-count throughput-optimized processor, similar to Xeon Phi.
> >
> > This arrangement would avoid the problems which appear when you mix low-latency cores with high-throughput
> > cores in a single socket, when the extra heat caused by AVX-256 or AVX-512 force the use of a lower
> > clock frequency, which slows down the threads where single-thread performance is important.
>
> Ice Lake and one of the Knights chips were supposed to sync in terms of ISA extensions, or be trivially
> close. The presumption was that Intel could release a heterogenous design. while they haven't said
> anything officially, it would be foolish to think that they haven't toyed with the concept internally.