Travis (travis.downs.delete@this.gmail.com) on August 4, 2018 1:50 pm wrote:
> I think Skylake client probably has most of the machinery needed for need for AVX-512, but it's just
> disabled/fused off[1]. For example I think it might very well have a 512-bit wide PRF. There were
> a lot of changes in Skylake client, including rearranging some port assignments and reducing the L2
> associativity that makes sense mostly if they wanted to re-use the same core for Skylake-SP.
> Also, take a look at these die shots:
> Skylake client:
>
> Skylake server (including uncore):
>

> Can someone who knows about this stuff point out the PRF? Maybe
> the regular blocks under the letter "OoO" in the first picture?
> You can see how the rectangular core part of the Skylake server die looks just like the Skylake client part,
> plus the "extra" AVX-512 EU and 768KiB of L2 cache hanging off the side mixed in with the uncore. So it
> looks very much like Skylake client was designed in mind already with this extension, which means that any
> part of the die inside the "core rectangle" in the server part would have already had all the transistors
> needed for AVX-512. In particular, it would have had 1 512-bit FMA unit (which isn't even anything else
> extra since that's just the two 256-bit FMAs it already has, stitched together). More importantly, it probably
> has all the in-core support for mask registers, the new AVX-512 instructions, etc, etc.
>
> I think that's why you get some cheaper Skylake-SP server chips with 1 FMA unit: they are
> the ones whose uncore doesn't have that extra AVX block hanging off the top. So in this
> case the missing FMA unit isn't arbitrary segmentation: it's actually a result of that EU
> hanging off the side of the main code and able to be omitted in some uncore designs.

Mustering all my mspaint skills, I think I would come to a different suspicion, if not necessarily final conclusion:


To my eye, the red section is roughly doubled in size on the server core, and there is a more regular visible fine grid structuring (at least in Fritz's original 63MB, 12k*8k px image) than in the presumptive execution units in the white boxes. I don't think that this is sufficient to conclusively label the PRF and not some other execution logic colocated with the FMACs, but the physical and storage sizes (~5 and ~10 kiB) seem sensible next to the 32 kiB L1D when you assume a moderate comparative density fudge factor. I think it is also perhaps more sensible to presume that the PRF would be adjacent to execution units to minimize routing delay, even if wider AVX clocking limits might come more from aggregate logic gate draw than critical path timings.

I poked around for about 10 min for a better die shot of client Skylake but unfortunately had no luck there, so all of this could still be easily disproved by better shot of the red box area on it.

All this said, there is definitely something in that general region that is bigger than on the client besides the block bolted on top. Intel could clearly have made the client chip support whatever level of AVX they wanted, but I am pretty sure this isn't some pure laser/eFuse job we're seeing.