New article: AMD's Jaguar Microarchitecture

Article: AMD's Jaguar Microarchitecture
By: Jeff Rupley (jrupley.delete@this.austin.rr.com), April 1, 2014 7:13 pm
Room: Moderated Discussions
SHK (nomail.delete@this.mail.com) on April 1, 2014 6:09 am wrote:
> Superb as always David, i'm gonna miss your m-arch deep-dive.
> On page 6 you say that the AGU has an adder and a multiplier but the index scaling part of the agen for
> the x86 is limited to 2x,4x,8x so i think it's rather a simple left shift not a full multiplier.
> Do you have any info on the implementation of the cmovcc instructions? Since i
> upgraded from an athlon-xp to a core-i7 i've always wondered why on snb cmovcc
> has a 2 clock latency while all my pervious AMD processor did it in 1 cycle.
>

cmov on Jaguar is decoded as 1 uop, w/ 1 cycle latency, can be executed on either ALU pipe.
Reference AMD's optimization table:
http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2012/10/AMD64_16h_InstrLatency_1.1.xlsx
Or search out Agner Fog's excellent optimization manuals.

-rupley
speaking only for myself
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