Article: AMD's Jaguar Microarchitecture
By: NaN (dontcare.delete@this.gmail.com), April 2, 2014 7:58 am
Room: Moderated Discussions
willmore (davidwillmore.delete@this.gmail.com) on April 1, 2014 6:37 pm wrote:
> Third page, second to last paragraph, second to last paragraph has:
> delta register by a dedicate ALU in the front-end
>
> Probably should be 'dedicated ALU'.
>
> Great article so far!
Page 5, bottom:
Yes, only x87 has instructions for integer division, but that is rather irrelevant. The 14-22 cycle latency most likely applies to floating point (single precision?) divison. Are denormals, infinities and NaNs handled without penalty, too?
> Third page, second to last paragraph, second to last paragraph has:
> delta register by a dedicate ALU in the front-end
>
> Probably should be 'dedicated ALU'.
>
> Great article so far!
Page 5, bottom:
Port 1 also executes FP division and square roots, re-using the multiplier circuitry and therefore blocking any multiply µops. Division is only available through the deprecated x87 instruction set and takes 14-22 cycles depending on the specific variant. [...]
Yes, only x87 has instructions for integer division, but that is rather irrelevant. The 14-22 cycle latency most likely applies to floating point (single precision?) divison. Are denormals, infinities and NaNs handled without penalty, too?