Limited operand tags in issue queue entries

Article: AMD's Jaguar Microarchitecture
By: Paul A. Clayton (paaronclayton.delete@this.gmail.com), April 2, 2014 1:32 pm
Room: Moderated Discussions
SHK (nomail.delete@this.mail.com) on April 2, 2014 12:17 pm wrote:
[snip]
> My understanding was that an AMD's macro-ops is something like a microfused ops (like add eax,
> [edi]), which is tracked as a single unit but cracked into multiple m-ops after issuing.
> I'm not sure how this could resolve the RAT problem you mentioned above.

The macro-ops do not deal with the "RAT problem" (which is handled simply by always writing to a destination register even if the value is unchanged). AMD's use of macro-ops apparently provides more than two operand tags with comparison logic to determine when an operation can begin execution (when all operands will be available).

(Conceptually, whenever an operation is selected to be executed, it sends its destination register name [typically only one per operation] to the scheduler which compares it with the tags for the operands of all instructions in the issue queue. If a tag matches the register name, that operand is marked as ready. If all operands are ready, the operation is ready to execute and may be selected to be executed. If only two tags are provided per operation (as was the case with Intel's designs [newer, three-operand instructions may have motivated Intel to change this]), then it is not possible for the issue queue entry to test availability of three operands. With macro-ops, providing more than two tags/comparators may make sense.)

Side comment: Another interesting aspect of using macro-ops is that it might be practical to avoid a temporary register (and a store data operation) for load-op-store instructions since the arithmetic operation could pass its result to the store queue directly. Since load-op-store instructions are uncommon, such an optimization is unlikely to be useful. (In principle, a similar optimization could be performed for any operation followed immediately by a storing of its result. This would not remove the need to write to the destination register but would avoid the need for a store data operation. This is effectively just fusing the store data operation with the computation operation.)
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