New article: AMD's Jaguar Microarchitecture

Article: AMD's Jaguar Microarchitecture
By: Brett (ggtgp.delete@this.yahoo.com), April 5, 2014 11:12 am
Room: Moderated Discussions
Michael S (already5chosen.delete@this.yahoo.com) on April 5, 2014 10:59 am wrote:
> Maynard Handley (name99.delete@this.name99.org) on April 5, 2014 10:38 am wrote:
> > UnmaskedUnderflow (whoawhoawhoa.delete@this.whoa.com) on April 4, 2014 11:45 am wrote:
> > > Linus Torvalds (torvalds.delete@this.linux-foundation.org) on April 4, 2014 8:54 am wrote:
> > - CPUs provide a very high performance "swap in/swap out FP state" instruction so that this is
> > just one more of those things that's done on entering/exiting a function and it gets lost in
> > the noise of incrementing the SP, storing the return address, and saving a few registers.
> > Advanced programming environments would allow this state to be toggled
> > at module entry/exit boundaries rather than per function.
> >
> > Unfortunately I am aware of no CPU+programming environment that thinks this way. Instead we
> > have the current totally retarded system where any random function along the way can toggle
> > FP state once and everyone else then suffers, OR a function has to swap the state in and out
> > on entry/exit, but the state swapping is uncomfortably slow --- and frequently unnecessary,
> > especially if the next function along is going to do the same damn state swapping.
>
> I don't follow.
> Why should one save/restore the whole FPU state, why not only FP control register? Saving/restoring
> only FPU control register is not slow relatively to the rest of library call overhead
> and it *should* be done by any library that wants to use non-default control bits. Anything
> less is bug and should not be tolerated bu library users.

You have ~100 instructions in the speculation queue and just changed the FPU mode, your FPU opcode picker is grabbing random instructions before and after the FPU mode change and executing them as load dependancies become available.

I would be some (most?) CPU's just flush the queue, expensive.
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