Article: AMD's Jaguar Microarchitecture
By: Michael S (already5chosen.delete@this.yahoo.com), April 8, 2014 4:05 pm
Room: Moderated Discussions
Wilco (Wilco.Dijkstra.delete@this.ntlworld.com) on April 8, 2014 2:56 pm wrote:
>
> Loads and stores are always done in the load-store units, there is no accelerator that executes memory accesses
> early in the pipeline. Typical use is read control register, clear some bits, set some bits, write control
> register. If there was an instruction "change rounding mode to round-to-even" then yes you could easily attach
> that to all FP ops during decode, but that is much harder for generic status register writes.
>
> Wilco
>
On Power and with respect to changing FP rounding mode Maynard's idea could actually work.
For example, mtfsfi 7,IMM is not exactly equivalent to "change rounding mode to imm[1..0]", but, for sake of brevity, sufficiently close to that.
>
> Loads and stores are always done in the load-store units, there is no accelerator that executes memory accesses
> early in the pipeline. Typical use is read control register, clear some bits, set some bits, write control
> register. If there was an instruction "change rounding mode to round-to-even" then yes you could easily attach
> that to all FP ops during decode, but that is much harder for generic status register writes.
>
> Wilco
>
On Power and with respect to changing FP rounding mode Maynard's idea could actually work.
For example, mtfsfi 7,IMM is not exactly equivalent to "change rounding mode to imm[1..0]", but, for sake of brevity, sufficiently close to that.