By: itsmydamnation (no.delete@this.way.com), May 6, 2014 10:12 pm
Room: Moderated Discussions
David Kanter (dkanter.delete@this.realworldtech.com) on May 6, 2014 1:33 pm wrote:
> Happy Wednesday,
>
> This is the first of one of my shorter posts at RWT. Rather than a grand, sprawling discourse on architecture,
> it is instead a much more focused discussion of singular but highly informative topic:
>
> "My favorite paper from the ISSCC processor session describes an adaptive clocking technique implemented
> in AMD’s 28nm Steamroller core that compensates for power supply noise. Initial results show
> a 10-20% decrease in power consumption from reducing the voltage, with no loss in performance.
> This elegant technique is likely to be adopted across AMD’s entire product line including GPUs,
> x86 CPUs, ARM-based CPUs, and other critical blocks in highly integrated SoCs."
>
> http://www.realworldtech.com/steamroller-clocking/
>
> As a personal aside, these sort of techniques are absolutely critical and what separate out the top-notch
> physical design groups from companies that slap together a pile of IP and call it an SoC.
>
> As always, comments and discussion are encouraged.
>
> David
Do you know if this was added in the new puma cores?
while there needs to be real world tests the puma cores are looking much better in perf per watt ( not just from the tubro). Something like this could be a contributor.
cheers
> Happy Wednesday,
>
> This is the first of one of my shorter posts at RWT. Rather than a grand, sprawling discourse on architecture,
> it is instead a much more focused discussion of singular but highly informative topic:
>
> "My favorite paper from the ISSCC processor session describes an adaptive clocking technique implemented
> in AMD’s 28nm Steamroller core that compensates for power supply noise. Initial results show
> a 10-20% decrease in power consumption from reducing the voltage, with no loss in performance.
> This elegant technique is likely to be adopted across AMD’s entire product line including GPUs,
> x86 CPUs, ARM-based CPUs, and other critical blocks in highly integrated SoCs."
>
> http://www.realworldtech.com/steamroller-clocking/
>
> As a personal aside, these sort of techniques are absolutely critical and what separate out the top-notch
> physical design groups from companies that slap together a pile of IP and call it an SoC.
>
> As always, comments and discussion are encouraged.
>
> David
Do you know if this was added in the new puma cores?
while there needs to be real world tests the puma cores are looking much better in perf per watt ( not just from the tubro). Something like this could be a contributor.
cheers
| Topic | Posted By | Date |
|---|---|---|
| New article: Adaptive Clocking in AMD’s Steamroller | David Kanter | 2014/05/06 12:33 PM |
| New article: Adaptive Clocking in AMD’s Steamroller | itsmydamnation | 2014/05/06 10:12 PM |
| New article: Adaptive Clocking in AMD’s Steamroller | Xi Yang | 2014/05/06 11:08 PM |
| Decoupling capacitors on GPUs | Gabriele Svelto | 2014/05/08 08:24 AM |
| Decoupling capacitors on GPUs | Ben | 2014/08/27 10:56 PM |
| New article: Adaptive Clocking in AMD’s Steamroller | Poindexter | 2014/05/10 05:06 PM |
| New article: Adaptive Clocking in AMD’s Steamroller | Rob Thorpe | 2014/05/12 04:42 AM |
| New article: Adaptive Clocking in AMD’s Steamroller | David Hess | 2014/05/12 09:02 AM |
| New article: Adaptive Clocking in AMD’s Steamroller | Rob Thorpe | 2014/05/12 09:46 AM |
| New article: Adaptive Clocking in AMD’s Steamroller | Ricardo B | 2014/05/13 02:15 AM |
| New article: Adaptive Clocking in AMD’s Steamroller | Rob Thorpe | 2014/05/13 05:30 AM |
| Multiple PLLs wouldn't work, but DLL jitter is no problem | Robyn Henry | 2014/05/13 11:58 PM |
