By: Rob Thorpe (rthorpe.delete@this.robertthorpeconsulting.com), May 12, 2014 5:42 am
Room: Moderated Discussions
David Kanter (dkanter.delete@this.realworldtech.com) on May 6, 2014 1:33 pm wrote:
> Happy Wednesday,
>
> This is the first of one of my shorter posts at RWT. Rather than a grand, sprawling discourse on architecture,
> it is instead a much more focused discussion of singular but highly informative topic:
I find it interesting that they use a DLL and a PLL to vary the clock speed. I think a better approach would be to have several PLLs constantly locked to different frequencies and to switch between them. Using an extra DLL in front of the PLL will add noise to the clock.
I agree with the discussion about capacitors. However, it's becoming easier to deploy MIM caps, I'm working on a product that uses them. Because MIM caps sit in the metal layers they don't necessarily impact area, other blocks can be put underneath them. Perhaps that's not true of power supply bypassing caps though because they give out E-field noise to the components beneath them. Even if you do have on-chip caps the value achievable are small compared to off-chip, this isn't a problem though if low-frequency noise isn't an issue.
> Happy Wednesday,
>
> This is the first of one of my shorter posts at RWT. Rather than a grand, sprawling discourse on architecture,
> it is instead a much more focused discussion of singular but highly informative topic:
I find it interesting that they use a DLL and a PLL to vary the clock speed. I think a better approach would be to have several PLLs constantly locked to different frequencies and to switch between them. Using an extra DLL in front of the PLL will add noise to the clock.
I agree with the discussion about capacitors. However, it's becoming easier to deploy MIM caps, I'm working on a product that uses them. Because MIM caps sit in the metal layers they don't necessarily impact area, other blocks can be put underneath them. Perhaps that's not true of power supply bypassing caps though because they give out E-field noise to the components beneath them. Even if you do have on-chip caps the value achievable are small compared to off-chip, this isn't a problem though if low-frequency noise isn't an issue.
| Topic | Posted By | Date |
|---|---|---|
| New article: Adaptive Clocking in AMD’s Steamroller | David Kanter | 2014/05/06 01:33 PM |
| New article: Adaptive Clocking in AMD’s Steamroller | itsmydamnation | 2014/05/06 11:12 PM |
| New article: Adaptive Clocking in AMD’s Steamroller | Xi Yang | 2014/05/07 12:08 AM |
| Decoupling capacitors on GPUs | Gabriele Svelto | 2014/05/08 09:24 AM |
| Decoupling capacitors on GPUs | Ben | 2014/08/27 11:56 PM |
| New article: Adaptive Clocking in AMD’s Steamroller | Poindexter | 2014/05/10 06:06 PM |
| New article: Adaptive Clocking in AMD’s Steamroller | Rob Thorpe | 2014/05/12 05:42 AM |
| New article: Adaptive Clocking in AMD’s Steamroller | David Hess | 2014/05/12 10:02 AM |
| New article: Adaptive Clocking in AMD’s Steamroller | Rob Thorpe | 2014/05/12 10:46 AM |
| New article: Adaptive Clocking in AMD’s Steamroller | Ricardo B | 2014/05/13 03:15 AM |
| New article: Adaptive Clocking in AMD’s Steamroller | Rob Thorpe | 2014/05/13 06:30 AM |
| Multiple PLLs wouldn't work, but DLL jitter is no problem | Robyn Henry | 2014/05/14 12:58 AM |
