New article: Adaptive Clocking in AMD’s Steamroller

Article: Adaptive Clocking in AMD's Steamroller
By: Ricardo B (ricardo.b.delete@this.xxxxx.xx), May 13, 2014 2:15 am
Room: Moderated Discussions
Rob Thorpe (rthorpe.delete@this.robertthorpeconsulting.com) on May 12, 2014 5:42 am wrote:
ive topic:
>
> I find it interesting that they use a DLL and a PLL to vary the clock speed. I think a better
> approach would be to have several PLLs constantly locked to different frequencies and to switch
> between them. Using an extra DLL in front of the PLL will add noise to the clock.

The jitter contribution of a well designed PLL will be <10 ps.
Probably, much less than the contribution of the clock distribution network.

The delay of switching between two slightly different PLL clocks will be larger, in the order of several cycles, to avoid run pulses and metastability conditions.

And to have a PLL produce several slightly different frequencies you're going to have to run the VCO and digital dividers at very high frequency.
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TopicPosted ByDate
New article: Adaptive Clocking in AMD’s SteamrollerDavid Kanter2014/05/06 12:33 PM
  New article: Adaptive Clocking in AMD’s Steamrolleritsmydamnation2014/05/06 10:12 PM
  New article: Adaptive Clocking in AMD’s SteamrollerXi Yang2014/05/06 11:08 PM
  Decoupling capacitors on GPUsGabriele Svelto2014/05/08 08:24 AM
    Decoupling capacitors on GPUsBen2014/08/27 10:56 PM
  New article: Adaptive Clocking in AMD’s SteamrollerPoindexter2014/05/10 05:06 PM
  New article: Adaptive Clocking in AMD’s SteamrollerRob Thorpe2014/05/12 04:42 AM
    New article: Adaptive Clocking in AMD’s SteamrollerDavid Hess2014/05/12 09:02 AM
      New article: Adaptive Clocking in AMD’s SteamrollerRob Thorpe2014/05/12 09:46 AM
    New article: Adaptive Clocking in AMD’s SteamrollerRicardo B2014/05/13 02:15 AM
      New article: Adaptive Clocking in AMD’s SteamrollerRob Thorpe2014/05/13 05:30 AM
    Multiple PLLs wouldn't work, but DLL jitter is no problemRobyn Henry2014/05/13 11:58 PM
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