Doug S (foo.delete@this.bar.bar) on August 4, 2014 8:14 pm wrote:
> Is that really a showstopper? Couldn't Apple design the memory controller on their SoC to be
> a buffer for Intel's memory controller? The x86 chip would think it is talking directly to
> the RAM, but it would be using a go-between. Similar to how buffered DIMMs work (I think)
>
> Its a performance hit, yes, but people aren't buying Macs for top performance anyway,
> so losing a few percent due to increased memory latency isn't really a big deal.
>

While technically possible, it doesn't really solve any problems. In that approach you would have to segment the memory between the two so that the arm side couldn't access any of the x86 side dimms/ranks in order to get the memory to work. And then you would have to somehow program the x86 memory controller so that you had spare time on the memory data lines for the arm access. Effectively you would just have a really expensive, low performance, complex system that was still basically just two separate memory systems.

The only way it could really work is to use a QPI enabled part but that puts you into a higher range of chips than is used for the vast majority of the mac line.