By: Gabriele Svelto (gabriele.svelto.delete@this.gmail.com), August 11, 2014 12:08 pm
Room: Moderated Discussions
anon (anon.delete@this.anon.com) on August 11, 2014 5:13 am wrote:
> I'm talking specifically about instruction decoding. Those restrictions in group formation
> and dispatch are due to limitations in other parts of the pipeline, and are in no
> way analogous to instruction type restrictions in Intel's x86 decoders.
On the contrary, group formation happens in the decoding stages, between early instruction decoding (ED stage) and the main decoding stage (Dcd stage). Check Figure 2-2 of the POWER8 user manual:
POWER8 Processor User’s Manual for the Single-Chip Module
Decoding of certain instructions (+4/+8 branches, move to special registers, load & store with update) which result in specific µop sequences have their own set of decoding limitations precisely because of this.
> I'm talking specifically about instruction decoding. Those restrictions in group formation
> and dispatch are due to limitations in other parts of the pipeline, and are in no
> way analogous to instruction type restrictions in Intel's x86 decoders.
On the contrary, group formation happens in the decoding stages, between early instruction decoding (ED stage) and the main decoding stage (Dcd stage). Check Figure 2-2 of the POWER8 user manual:
POWER8 Processor User’s Manual for the Single-Chip Module
Decoding of certain instructions (+4/+8 branches, move to special registers, load & store with update) which result in specific µop sequences have their own set of decoding limitations precisely because of this.