Maynard Handley (name99.delete@this.name99.org) on August 16, 2014 2:24 pm wrote:
> Likewise for synchronization primitives. The consensus as I read the literature is
> that load locked/store conditional is substantially easier to implement and get right
> than LOCK prefixes and the random mix of other things that Intel has. I'm guessing
> it's then also easier to build HW TM on top of load locked/store conditional.
> Beyond this, I'm guessing it's substantially harder to design for and verify
> the Intel memory model than the looser POWER and ARM memory models.
>
Actually, many software people have come to mostly loathe LL/SC and its been involved an lots of bugs of either software or hardware over the years. The truth is that LL/SC is pretty much only used for effectively CMPXHG.

And its generally easier to design and verify for the x86 MOM than for any of the more relaxed memory models. Esp from a software perspective. And from a performance perspective, because of the software issues, the stricter MOMs tend to have better performance. AKA with a weaker MOM, software developers tend to be much more cautious which leads to lower performance. So far, the performance/strictness relationship with MOMs has been a case of Theory != Practice.

Maynard, you've been around long enough that you've almost certainly seen Linus rant #X on this topic. This is definitely one of those areas where I agree with Linus. Make it easier for the programmers, hardware designers be dammed.